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MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Order this document by MC68HC11KA4TS/D
M68HC11 KA Series
Technical Summary 8-Bit Microcontroller
1 Introduction
The MC68HC11KA4 family of microcontrollers are enhanced derivatives of the MC68HC11F1 and, as shown in the block diagram, include many additional features. The family includes the MC68HC11KA0, MC68HC11KA1, MC68HC11KA3, MC68HC11KA4, MC68HC711KA4, MC68HC11KA2, and the MC68HC711KA2. These MCUs, with a non-multiplexed expanded bus, are characterized by high speed and low power consumption. The fully static design allows operation at frequencies from 4 MHz to dc. This technical summary contains information concerning standard, custom-ROM, and extended-voltage devices. Standard devices are those with disabled ROM (MC68HC11KA1), disabled EEPROM (MC68HC11KA0), and EPROM replacing ROM (MC68HC711KA4). The MC68HC11KA2 and MC68HC711KA2 contain 32 Kbytes of ROM/EPROM instead of 24 Kbytes. Custom-ROM devices have a ROM array that is programmed at the factory to customer specifications. Extended-voltage devices are guaranteed to operate over a much greater voltage range (3.0 Vdc to 5.5 Vdc) at lower frequencies than the standard devices. Refer to the ordering information on the following pages. In this summary, ROM/EPROM refers to ROM for ROM-based devices and refers to EPROM for EPROM-based devices. 1.1 Features * M68HC11 Central Processing Unit (CPU) * Power Saving STOP and WAIT Modes * 768 Bytes RAM in MC68HC11KA4, 1024 Bytes RAM in MC68HC11KA2 (Saved During Standby) * 640 Bytes Electrically Erasable Programmable ROM (EEPROM) * 24 Kbytes ROM/EPROM, 32 Kbytes ROM/EPROM in MC68HC11KA2 * PROG Mode Allows Use of Standard EPROM Programmer (27256 Footprint) * Non-multiplexed Address and Data Buses * Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler -- Three Input Capture (IC) Channels -- Four Output Compare (OC) Channels -- One Additional Channel, Selectable as Fourth IC or Fifth OC * 8-Bit Pulse Accumulator * Four 8-Bit or Two 16-Bit Pulse-Width Modulation (PWM) Timer Channels * Real-Time Interrupt Circuit * Computer Operating Properly (COP) Watchdog * Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI) * Enhanced Synchronous Serial Peripheral Interface (SPI) * Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter (Four Channels on 64-Pin Version) * Seven Bidirectional Input/Output (I/O) Ports (43 Pins) * One Fixed Input-Only Port (8 Pins, 4 Pins on 64-Pin Version) * Available in 68-Pin Plastic Leaded Chip Carrier (Custom ROM/OTPROM), 68-Pin Windowed Ceramic Leaded Chip Carrier (EPROM), or 64-Pin Quad Flat Pack (Custom ROM/OTPROM)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) MOTOROLA INC., 1996
Table 1 Standard Device Ordering Information
Package 68-Pin Plastic Leaded Chip Carrier Temperature -40 + 85C -40to + 85C CONFIG $DF $DD Description BUFFALO ROM No ROM Frequency 4 MHz 2 MHz 3 MHz 4 MHz -40to + 105C $DD No ROM 2 MHz 3 MHz 4 MHz -40to + 125C $DD No ROM 2 MHz 3 MHz 4 MHz -40to + 85C $DC No ROM, No EEPROM 2 MHz 3 MHz 4 MHz -40to + 105C $DC No ROM, No EEPROM 2 MHz 3 MHz 4 MHz -40to + 125C $DC No ROM, No EEPROM 2 MHz 3 MHz 4 MHz -40to + 85C $DF 24 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 105C $DF 24 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 125C $DF 24 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 85C $DF 32 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 105C $DF 32 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 125C $DF 32 Kbytes OTPROM 2 MHz 3 MHz 4 MHz MC Order Number MC68HC11KA4BCFN4 MC68HC11KA1CFN2 MC68HC11KA1CFN3 MC68HC11KA1CFN4 MC68HC11KA1VFN2 MC68HC11KA1VFN3 MC68HC11KA1VFN4 MC68HC11KA1MFN2 MC68HC11KA1MFN3 MC68HC11KA1MFN4 MC68HC11KA0CFN2 MC68HC11KA0CFN3 MC68HC11KA0CFN4 MC68HC11KA0VFN2 MC68HC11KA0VFN3 MC68HC11KA0VFN4 MC68HC11KA0MFN2 MC68HC11KA0MFN3 MC68HC11KA0MFN4 MC68HC711KA4CFN2 MC68HC711KA4CFN3 MC68HC711KA4CFN4 MC68HC711KA4VFN2 MC68HC711KA4VFN3 MC68HC711KA4VFN4 MC68HC711KA4MFN2 MC68HC711KA4MFN3 MC68HC711KA4MFN4 MC68HC711KA2CFN2 MC68HC711KA2CFN3 MC68HC711KA2CFN4 MC68HC711KA2VFN2 MC68HC711KA2VFN3 MC68HC711KA2VFN4 MC68HC711KA2MFN2 MC68HC711KA2MFN3 MC68HC711KA2MFN4
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MC68HC11KA4 MC68HC11KA4TS/D
Table 1 Standard Device Ordering Information (Continued)
Package 64-Pin Quad Flat Pack Temperature -40to + 85C -40to + 85C CONFIG $DF $DF Description BUFFALO ROM 24 Kbytes OTPROM Frequency 4 MHz 2 MHz 3 MHz 4 MHz -40to + 105C $DF 24 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 125C $DF 24 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 85C $DF 32 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 105C $DF 32 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 125C $DF 32 Kbytes OTPROM 2 MHz 3 MHz 4 MHz -40to + 85C $DD No ROM 2 MHz 3 MHz 4 MHz -40to + 105C $DD No ROM 2 MHz 3 MHz 4 MHz -40to + 85C $DC No ROM, No EEPROM 2 MHz 3 MHz 4 MHz -40to + 105C $DC No ROM, No EEPROM 2 MHz 3 MHz 4 MHz MC Order Number MC68HC11KA4BCFU4 MC68HC711KA4CFU2 MC68HC711KA4CFU3 MC68HC711KA4CFU4 MC68HC711KA4VFU2 MC68HC711KA4VFU3 MC68HC711KA4VFU4 MC68HC711KA4MFU2 MC68HC711KA4MFU3 MC68HC711KA4MFU4 MC68HC711KA2CFU2 MC68HC711KA2CFU3 MC68HC711KA2CFU4 MC68HC711KA2VFU2 MC68HC711KA2VFU3 MC68HC711KA2VFU4 MC68HC711KA2MFU2 MC68HC711KA2MFU3 MC68HC711KA2MFU4 MC68HC11KA1CFU2 MC68HC11KA1CFU3 MC68HC11KA1CFU4 MC68HC11KA1VFU2 MC68HC11KA1VFU3 MC68HC11KA1VFU4 MC68HC11KA0CFU2 MC68HC11KA0CFU3 MC68HC11KA0CFU4 MC68HC11KA0VFU2 MC68HC11KA0VFU3 MC68HC11KA0VFU4
MC68HC11KA4 MC68HC11KA4TS/D
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Table 1 Standard Device Ordering Information (Continued)
Package 68-Pin Cerquad Temperature -40to + 85C CONFIG $DF Description 24 Kbytes EPROM Frequency 2 MHz 3 MHz 4 MHz -40to + 105C $DF 24 Kbytes EPROM 2 MHz 3 MHz 4 MHz -40to + 125C $DF 24 Kbytes EPROM 2 MHz 3 MHz 4 MHz -40to + 85C $DF 32 Kbytes EPROM 2 MHz 3 MHz 4 MHz -40to + 105C $DF 32 Kbytes EPROM 2 MHz 3 MHz 4 MHz -40to + 125C $DF 32 Kbytes EPROM 2 MHz 3 MHz 4 MHz MC Order Number MC68HC711KA4CFS2 MC68HC711KA4CFS3 MC68HC711KA4CFS4 MC68HC711KA4VFS2 MC68HC711KA4VFS3 MC68HC711KA4VFS4 MC68HC711KA4MFS2 MC68HC711KA4MFS3 MC68HC711KA4MFS4 MC68HC711KA2CFS2 MC68HC711KA2CFS3 MC68HC711KA2CFS4 MC68HC711KA2VFS2 MC68HC711KA2VFS3 MC68HC711KA2VFS4 MC68HC711KA2MFS2 MC68HC711KA2MFS3 MC68HC711KA2MFS4
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MC68HC11KA4 MC68HC11KA4TS/D
Table 2 Custom ROM Device Ordering Information
Package 68-Pin Plastic Leaded Chip Carrier Temperature -40to + 85C Description 24 Kbytes Custom ROM Frequency 2 MHz 3 MHz 4 MHz -40to + 105C 24 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz -40to + 125C 24 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz -40to + 85C 32 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz -40to + 105C 32 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz -40to + 125C 32 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz -40to + 85C 24 Kbytes Custom ROM, No EEPROM -40to + 105C 24 Kbytes Custom ROM, No EEPROM -40to + 125C 24 Kbytes Custom ROM, No EEPROM 2 MHz 3 MHz 4 MHz 2 MHz 3 MHz 4 MHz 2 MHz 3 MHz 4 MHz MC Order Number MC68HC11KA4CFN2 MC68HC11KA4CFN3 MC68HC11KA4CFN4 MC68HC11KA4VFN2 MC68HC11KA4VFN3 MC68HC11KA4VFN4 MC68HC11KA4MFN2 MC68HC11KA4MFN3 MC68HC11KA4MFN4 MC68HC11KA2CFN2 MC68HC11KA2CFN3 MC68HC11KA2CFN4 MC68HC11KA2VFN2 MC68HC11KA2VFN3 MC68HC11KA2VFN4 MC68HC11KA2MFN2 MC68HC11KA2MFN3 MC68HC11KA2MFN4 MC68HC11KA3CFN2 MC68HC11KA3CFN3 MC68HC11KA3CFN4 MC68HC11KA3VFN2 MC68HC11KA3VFN3 MC68HC11KA3VFN4 MC68HC11KA3MFN2 MC68HC11KA3MFN3 MC68HC11KA3MFN4
MC68HC11KA4 MC68HC11KA4TS/D
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Table 2 Custom ROM Device Ordering Information (Continued)
Package 64-Pin Quad Flat Pack Temperature -40to + 85C Description 24 Kbytes Custom ROM Frequency 2 MHz 3 MHz 4 MHz -40to + 105C 24 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz -40to + 85C 32 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz -40to + 105C 32 Kbytes Custom ROM 2 MHz 3 MHz 4 MHz -40to + 85C 24 Kbytes Custom ROM, No EEPROM -40to + 105C 24 Kbytes Custom ROM, No EEPROM 2 MHz 3 MHz 4 MHz 2 MHz 3 MHz 4 MHz MC Order Number MC68HC11KA4CFU2 MC68HC11KA4CFU3 MC68HC11KA4CFU4 MC68HC11KA4VFU2 MC68HC11KA4VFU3 MC68HC11KA4VFU4 MC68HC11KA2CFU2 MC68HC11KA2CFU3 MC68HC11KA2CFU4 MC68HC11KA2VFU2 MC68HC11KA2VFU3 MC68HC11KA2VFU4 MC68HC11KA3CFU2 MC68HC11KA3CFU3 MC68HC11KA3CFU4 MC68HC11KA3VFU2 MC68HC11KA3VFU3 MC68HC11KA3VFU4
Table 3 Extended Voltage (3.0 Vdc to 5.5 Vdc) Device Ordering Information
Package 68-Pin Plastic Leaded Chip Carrier Temperature -20to + 70C Description 24 Kbytes Custom ROM 32 Kbytes Custom ROM No ROM No ROM, No EEPROM 24 Kbytes Custom ROM, No EEPROM 64-Pin Quad Flat Pack -20to + 70C 24 Kbytes Custom ROM 32 Kbytes Custom ROM No ROM No ROM, No EEPROM 24 Kbytes Custom ROM, No EEPROM Frequency 1 MHz 3 MHz 1 MHz 3 MHz 1 MHz 3 MHz 1 MHz 3 MHz 1 MHz 3 MHz 1 MHz 3 MHz 1 MHz 3 MHz 1 MHz 3 MHz 1 MHz 3 MHz 1 MHz 3 MHz MC Order Number MC68L11KA4FN1 MC68L11KA4FN3 MC68L11KA2FN1 MC68L11KA2FN3 MC68L11KA1FN1 MC68L11KA1FN3 MC68L11KA0FN1 MC68L11KA0FN3 MC68L11KA3FN1 MC68L11KA3FN3 MC68L11KA4FU1 MC68L11KA4FU3 MC68L11KA2FU1 MC68L11KA2FU3 MC68L11KA1FU1 MC68L11KA1FU3 MC68L11KA0FU1 MC68L11KA0FU3 MC68L11KA3FU1 MC68L11KA3FU3
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MC68HC11KA4 MC68HC11KA4TS/D
PA0/IC3 PA1/IC2 PA2/IC1 PA3/OC5/IC4/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 VDDINT VDDEXT VSSEXT 9 8 7 6 5 4 3 2
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD
PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PH0/PW1 PH1/PW2 PH2/PW3 PH3/PW4 XIRQ/VPPE* PG7/R/W IRQ AVDD PE7/AN7
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1
MC68HC(7)11KA4 MC68HC(7)11KA2
MODA/LIR MODB/VSTBY RESET XTAL EXTAL XOUT E PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 PF0/ADDR0 PF1/ADDR1
* VPPE applies to MC68HC711KA4 and MC68HC711KA2 only.
Figure 1 Pin Assignments for 68-Pin Plastic Leaded Chip Carrier/Cerquad
MC68HC11KA4 MC68HC11KA4TS/D
PE6/AN6 PE5/AN5 PE4/AN4 PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0 VRL VRH AVSS VSSINT PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3 PF2/ADDR2
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
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64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PD0/RxD MODA/LIR MODB/VSTBY RESET XTAL EXTAL E PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 PF0/ADDR0
PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS VSS VDD VDD PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/IC4/OC1 PA2/IC1 PA1/IC2 PA0/IC3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MC68HC(7)11KA4 MC68HC(7)11KA2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PF1/ADDR1 PF2/ADDR2 PF3/ADDR3 PF4/ADDR4 PF5/ADDR5 PF6/ADDR6 PF7/ADDR7 VSS AVSS VRH VRL PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 VSS
* VPPE applies to MC68HC711KA4 and MC68HC711KA2 only.
Figure 2 Pin Assignments for 64-Pin Quad Flat Pack
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PB7/ADDR15 PB6/ADDR14 PB5/ADDR13 PB4/ADDR12 PB3/ADDR11 PB2/ADDR10 PB1/ADDR9 PB0/ADDR8 PH0/PW1 PH1/PW2 PH2/PW3 PH3/PW4 XIRQ/VPPE* PG7/R/W IRQ AVDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
MC68HC11KA4 MC68HC11KA4TS/D
XTAL EXTAL E XOUT2 MODA/ LIR MODB/ VSTBY PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORT A PORT A DDR PULSE PAI/OC1 ACCUMULATOR OC2/OC1 OC3/OC1 OC4/OC1 OC5/IC4/OC1 IC1 IC2 IC3 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 R/W TIMER SYSTEM OSCILLATOR MODE CONTROL CLOCK LOGIC
INTERRUPT LOGIC VRH VRL AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVDD AVSS
IRQ XIRQ/VPPE1 RESET VRH VRL PE7 PE6 2 PE5 PE4 PE3 PE2 PE1 PE0 AVDD AVSS VDD VSS VDD VSS
COP
PERIODIC INTERRUPT A/D CONVERTER
INTERNAL
EXTERNAL
PORT B PORT B DDR
ADDRESS BUS
PORT F PORT F DDR
CPU
1024 BYTES RAM (KA2)
32 KBYTES ROM/ EPROM (KA2)
640 BYTES EEPROM (KA1, KA4, KA2)
PW4 PW3 PW2 PW1
PORT H DDR PORT H
24 768 KBYTES BYTES ROM/ RAM EPROM (KA0, KA1, (KA3, KA4) KA3, KA4)
PWM PH3 PH2 PH1 PH0
PORT E
PORT D DDR PORT D
SPI
SS SCK MOSI MISO
PD5 PD4 PD3 PD2
PORT C PORT C DDR
DATA BUS
SCI
TxD RxD
PD1 PD0 PG7
NOTES: 1. VPPE applies to MC68HC711KA4 and MC68HC711KA2 only. 2. Not bonded on 64-pin version.
Figure 3 MC68HC11KA4/MC68HC711KA4 Block Diagram
MC68HC11KA4 MC68HC11KA4TS/D
PORT G DDR PORT G
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TABLE OF CONTENTS
Section Page
1
1.1
Introduction
2.1 2.2
2 3 4 5 6 7 8 9 10
10.1
11 12
1 Features ......................................................................................................................................1 Operating Modes and On-Chip Memory 11 Operating Modes .......................................................................................................................11 On-Chip Memory .......................................................................................................................11 Erasable Programmable Read-Only Memory 21 Electrically Erasable Programmable Read-Only Memory 23 Resets and Interrupts 26 Parallel Input/Output 31 Serial Communications Interface 37 Serial Peripheral Interface 44 Analog-to-Digital Converter 48 Main Timer 52 Real-Time Interrupt ...................................................................................................................58 Pulse Accumulator 59 Pulse-Width Modulation Timer 62
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MC68HC11KA4 MC68HC11KA4TS/D
2 Operating Modes and On-Chip Memory
2.1 Operating Modes In single-chip operating mode, the MC68HC11KA4 is a stand-alone microcontroller with no external address or data bus. In expanded non-multiplexed operating mode, the MCU can access a 64 Kbyte physical address space. This space includes the same on-chip memory addresses used for single-chip mode, in addition to addressing capabilities for external peripheral and memory devices. The expansion bus is made up of ports B, C, and F, and the R/W signal. In expanded operating mode, high order address bits are output on the port B pins, low order address bits on the port F pins, and the data bus on port C. The R/W pin controls the direction of data transfer on the port C bus. Bootstrap mode allows special-purpose programs to be entered into internal RAM. The bootloader program uses the serial communications interface (SCI) to read a program of up to 768 bytes into on-chip RAM. After a four-character delay, or after receiving the character for address $037F ($047F for MC68HC11KA2), control passes to the loaded program at $0080. Special test mode is used primarily for factory testing. 2.2 On-Chip Memory The M68HC11 CPU is capable of addressing a 64 Kbyte range. The INIT, INIT2, and CONFIG registers control the existence and locations of the registers, RAM, EEPROM, and ROM in the physical 64 Kbyte memory space. Addressing beyond the 64 Kbyte range is possible using a memory paging scheme in expanded mode only. The 128-byte register block originates at $0000 after reset and can be placed at any other 4 Kbyte boundary ($x000) after reset by writing an appropriate value to the INIT register. The 768-byte RAM (1024 bytes in the MC68HC11KA2) can be remapped to any 4 Kbyte boundary in memory. The RAM in the MC68HC11KA4 is divided into two sections of 128 bytes and 640 bytes. For the MC68HC11KA4, 128 bytes of the RAM are mapped at $0000-$007F unless the registers are mapped to this space. If the registers are located in this space, the same 128 bytes of RAM are located at $0300 to $037F. The RAM in the MC68HC11KA2 is divided into two sections of 128 bytes and 896 bytes. For the MC68HC11KA2, 128 bytes of the RAM are mapped at $0000-$007F unless the registers are mapped to this space. If the registers are located in this space, the same 128 bytes of RAM are located at $0300 to $047F. Remapping is accomplished by writing appropriate values into the two nibbles of the INIT register. Refer to the register and RAM mapping examples following the MC68HC11KA4 and MC68HC11KA2 memory maps. The 640-byte EEPROM is initially located at $0D80 after reset, assuming EEPROM is enabled in the memory map by the CONFIG register. EEPROM can be placed at any other 4 Kbyte boundary ($xD80) by writing appropriate values to the INIT2 register. The ROMAD and ROMON control bits in the CONFIG register control the position and presence of ROM/EPROM in the memory map. In special test mode, the ROMON bit is forced to zero so that the ROM/EPROM is removed from the memory map. In single-chip mode, the ROMAD bit is forced to one, causing the ROM/EPROM to be enabled at $A000-$FFFF ($8000-$FFFF in the MC68HC11KA2). This guarantees that there will be ROM/EPROM at the vector space.
MC68HC11KA4 MC68HC11KA4TS/D
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$0000
0000 EXT EXT 007F 0080 037F EXT EXT 0D80 0FFF
128-BYTE REGISTER BLOCK (CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT REGISTER) 768 BYTES RAM (NOTE 2) (CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT REGISTER) 640 BYTES EEPROM (CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT2 REGISTER) BE00 BFC0 BFFF BOOT ROM (ONLY PRESENT IN BOOTSTRAP MODE) SPECIAL MODE INTERRUPT VECTORS
$1000
$A000
A000
24 KBYTES ROM/EPROM (NOTE 3) (CAN BE REMAPPED TO $2000-$7FFF OR $A000-$FFFF BY THE CONFIG REGISTER) FFC0 $FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST FFFF FFFF NORMAL MODE INTERRUPT VECTORS
NOTES: 1. EPROM can be enabled in special test mode by setting the ROMON bit in the config register after reset. 2. 768 bytes RAM in MC68HC711KA4, 1024 bytes RAM in MC68HC711KA2. 3. 24 Kbytes ROM/EPROM in MC68HC711KA4, 32 Kbytes ROM/EPROM in MC68HC711KA2.
Figure 4 Memory Map for MC68HC11KA4
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MC68HC11KA4 MC68HC11KA4TS/D
$0000
0000 EXT EXT 007F 0080 047F EXT EXT 0D80 0FFF
128-BYTE REGISTER BLOCK (CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT REGISTER) 1024 BYTES RAM (NOTE 2) (CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT REGISTER) 640 BYTES EEPROM (CAN BE REMAPPED TO ANY 4K PAGE BY THE INIT2 REGISTER) BE00 BFC0 BFFF BOOT ROM (ONLY PRESENT IN BOOTSTRAP MODE) SPECIAL MODE INTERRUPT VECTORS
$1000
$8000
8000
32 KBYTES ROM/EPROM (NOTE 3) (CAN BE REMAPPED TO $0000-$7FFF OR $8000-$FFFF BY THE CONFIG REGISTER) FFC0 $FFFF SINGLE CHIP EXPANDED BOOTSTRAP SPECIAL TEST FFFF FFFF NORMAL MODE INTERRUPT VECTORS
NOTES: 1. EPROM can be enabled in special test mode by setting the ROMON bit in the config register after reset. 2. 768 bytes RAM in MC68HC711KA4, 1024 bytes RAM in MC68HC711KA2. 3. 24 Kbytes ROM/EPROM in MC68HC711KA4, 32 Kbytes ROM/EPROM in MC68HC711KA2.
Figure 5 Memory Map for MC68HC11KA2
MC68HC11KA4 MC68HC11KA4TS/D
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INIT = $00 REG @ $0000 RAM @ $0080 $0000 REGISTER BLOCK (128 BYTES) $007F $0080
INIT = $10 REG @ $0000 RAM @ $1000 $0000 REGISTER BLOCK (128 BYTES) $007F
INIT = $04 REG @ $4000 RAM @ $0000 $0000 RAM A (128 BYTES) $007F $0080
$1000 RAM B (640 BYTES) $02FF $0300 RAM A (128 BYTES) $037F RAM A (128 BYTES) $107F $1080 RAM B (640 BYTES) $12FF
RAM B (640 BYTES) $02FF
$4000 REGISTER BLOCK (128 BYTES) $407F
Figure 6 RAM and Register Mapping for MC68HC11KA4
INIT = $00 REG @ $0000 RAM @ $0080 $0000 REGISTER BLOCK (128 BYTES) $007F $0080
INIT = $10 REG @ $0000 RAM @ $1000 $0000 REGISTER BLOCK (128 BYTES) $007F
INIT = $04 REG @ $4000 RAM @ $0000 $0000 RAM A (128 BYTES) $007F $0080
$1000 RAM B (896 BYTES) $03FF $0400 RAM A (128 BYTES) $047F RAM A (128 BYTES) $107F $1080 RAM B (896 BYTES) $13FF
RAM B (896 BYTES) $03FF
$4000 REGISTER BLOCK (128 BYTES) $407F
Figure 7 RAM and Register Mapping for MC68HC11KA2
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MC68HC11KA4 MC68HC11KA4TS/D
Table 4 MC68HC11KA4 Register and Control Bit Assignments
Bit 7 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B PA7 DDA7 DDB7 DDF7 PB7 PF7 PC7 DDC7 0 0 PE7 FOC1 OC1M7 OC1D7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 OM2 EDG4B OC1I OC1F TOI TOF 0 Bit 7 SPIE SPIF Bit 7 MBE 6 PA6 DDA6 DDB6 DDF6 PB6 PF6 PC6 DDC6 0 0 PE6 FOC2 OC1M6 OC1D6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 14 6 OL2 EDG4A OC2I OC2F RTII RTIF PAEN 6 SPE WCOL 6 0 5 PA5 DDA5 DDB5 DDF5 PB5 PF5 PC5 DDC5 PD5 DDD5 PE5 FOC3 OC1M5 OC1D5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 13 5 OM3 EDG1B OC3I OC3F PAOVI PAOVF PAMOD 5 DWOM 0 5 ELAT 4 PA4 DDA4 DDB4 DDF4 PB4 PF4 PC4 DDC4 PD4 DDD4 PE4 FOC4 OC1M4 OC1D4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 12 4 OL3 EDG1A OC4I OC4F PAII PAIF PEDGE 4 MSTR MODF 4 EXCOL 3 PA3 DDA3 DDB3 DDF3 PB3 PF3 PC3 DDC3 PD3 DDD3 PE3 FOC5 OC1M3 OC1D3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 11 3 OM4 EDG2B I4/O5I I4/O5F 0 0 0 3 CPOL 0 3 EXROW 2 PA2 DDA2 DDB2 DDF2 PB2 PF2 PC2 DDC2 PD2 DDD2 PE2 0 0 0 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 10 2 OL4 EDG2A IC1I IC1F 0 0 I4/O5 2 CPHA 0 2 0 1 PA1 DDA1 DDB1 DDF1 PB1 PF1 PC1 DDC1 PD1 DDD1 PE1 0 0 0 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 9 1 OM5 EDG3B IC2I IC2F PR1 0 RTR1 1 SPR1 0 1 0 Bit 0 PA0 DDA0 DDB0 DDF0 PB0 PF0 PC0 DDC0 PD0 DDD0 PE0 0 0 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 OL5 EDG3A IC3I IC3F PR0 0 RTR0 Bit 0 SPR0 0 Bit 0 EPGM PORTA DDRA DDRB DDRF PORTB PORTF PORTC DDRC PORTD DDRD PORTE CFORC OC1M OC1D TCNT (High) TCNT (Low) TIC1 (High) TIC1 (Low) TIC2 (High) TIC2 (Low) TIC3 (High) TIC3 (Low) TOC1(High) TOC1 (Low) TOC2 (High) TOC2 (Low) TOC3 (High) TOC3 (Low) TOC4 (High) TOC4 (Low) TI4/O5 (High) TI4/O5 (Low) TCTL1 TCTL2 TMSK1 TFLG1 TMSK2 TFLG2 PACTL PACNT SPCR SPSR SPDR EPROG
MC68HC11KA4 MC68HC11KA4TS/D
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Table 4 MC68HC11KA4 Register and Control Bit Assignments (Continued)
Bit 7 $002C $002D $002E $002F $0030 $0031 $0032 $0033 $0034 $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F $0040 to $005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 $0068 $0069 $006A $006B $006C $006D $006E $006F $0070 $0071 $0072 $0073 $0074 $0075 -- CON34 PCLK4 Bit 7 TPWSL Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 BTST SBR7 LOOPS TIE TDRE 0 -- CON12 PCLK3 6 DISCP 6 6 6 6 6 6 6 6 6 6 6 6 BSPL SBR6 WOMS TCIE TC 0 -- PCKA2 PCLK2 5 0 5 5 5 5 5 5 5 5 5 5 5 5 0 SBR5 0 RIE RDRF 0 -- PCKA1 PCLK1 4 0 4 4 4 4 4 4 4 4 4 4 4 4 SBR12 SBR4 M ILIE IDLE 0 -- 0 PPOL4 3 PWEN4 3 3 3 3 3 3 3 3 3 3 3 3 SBR11 SBR3 WAKE TE OR 0 -- PCKB3 PPOL3 2 PWEN3 2 2 2 2 2 2 2 2 2 2 2 2 SBR10 SBR2 ILT RE NF 0 -- PCKB2 PPOL2 1 PWEN2 1 1 1 1 1 1 1 1 1 1 1 1 SBR9 SBR1 PE RWU FE 0 -- PCKB1 PPOL1 Bit 0 PWEN1 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 SBR8 SBR0 PT SBK PF RAF Reserved PWCLK PWPOL PWSCAL PWEN PWCNT1 PWCNT2 PWCNT3 PWCNT4 PWPER1 PWPER2 PWPER3 PWPER4 PWDTY1 PWDTY2 PWDTY3 PWDTY4 SCBDH SCBDL SCCR1 SCCR2 SCSR1 SCSR2 0 -- -- -- CCF Bit 7 Bit 7 Bit 7 Bit 7 BULKP -- EE3 LIRDV ADPU Bit 7 ODD RBOOT RAM3 TILOP ROMAD -- 6 0 -- -- -- 0 6 6 6 6 LVPEN -- EE2 CWOM CSEL 6 EVEN SMOD RAM2 0 1 -- 5 0 -- -- -- SCAN 5 5 5 5 BPRT4 -- EE1 0 IRQE 5 LVPI MDA RAM1 OCCR CLKX -- 4 0 -- -- -- MULT 4 4 4 4 PTCON -- EE0 IRVNE DLY 4 BYTE PSEL4 RAM0 CBYP PAREN -- 3 HPPUE -- -- -- CD 3 3 3 3 BPRT3 -- 0 LSBF CME 3 ROW PSEL3 REG3 DISR NOSEC -- 2 GPPUE -- -- -- CC 2 2 2 2 BPRT2 -- 0 SPR2 FCME 2 ERASE PSEL2 REG2 FCM NOCOP -- 1 FPPUE -- -- -- CB 1 1 1 1 BPRT1 -- 0 XDV1 CR1 1 EELAT PSEL1 REG1 FCOP ROMON -- Bit 0 BPPUE -- -- -- CA Bit 0 Bit 0 Bit 0 Bit 0 BPRT0 -- 0 XDV0 CR0 Bit 0 EEPGM PSEL0 REG0 0 EEON -- PPAR Reserved Reserved Reserved ADCTL ADR1 ADR2 ADR3 ADR4 BPROT Reserved INIT2 OPT2 OPTION COPRST PPROG HPRIO INIT TEST1 CONFIG Reserved
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MC68HC11KA4 MC68HC11KA4TS/D
Table 4 MC68HC11KA4 Register and Control Bit Assignments (Continued)
Bit 7 $0076 $0077 $0078 to $007B $007C $007D $007E $007F -- 0 0 PG7 DDG7 -- 0 0 0 0 -- 0 0 0 0 -- 0 0 0 0 -- PH3 DDH3 0 0 -- PH2 DDH2 0 0 -- PH1 DDH1 0 0 -- PH0 DDH0 0 0 Reserved PORTH DDRH PORTG DDRG R8 R7/T7 -- 6 T8 R6/T6 -- 5 0 R5/T5 -- 4 0 R4/T4 -- 3 0 R3/T3 -- 2 0 R2/T2 -- 1 0 R1/T1 -- Bit 0 0 R0/T0 -- SCDRH SCDRL Reserved
HPRIO -- Highest Priority I-Bit Interrupt and Miscellaneous
Bit 7 6 5 MDA* 0 1 0 1 4 PSEL4 0 0 0 0 3 2 1 Bit 0
$003C
RBOOT* SMOD* RESET: 0 0 1 0 0 0 1 1
PSEL3 PSEL2 PSEL1 PSEL0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Single Chip Expanded Bootstrap Special Test
*The reset values of RBOOT, SMOD, and MDA depend on the mode selected at power up.
RBOOT -- Read Bootstrap ROM Valid only when SMOD is set to one (bootstrap or special test mode). Can only be written in special mode. 0 = Bootloader ROM disabled and not in map 1 = Bootloader ROM enabled and in map at $BE00-$BFFF SMOD and MDA --Special Mode Select and Mode Select A These two bits can be read at any time. SMOD can only be written to zero. MDA can only be written once in normal modes or any time in special modes.
Inputs MODB 1 1 0 0 MODA 0 1 0 1 Mode Single Chip Expanded Bootstrap Special Test Latched at Reset SMOD 0 0 1 1 MDA 0 1 0 1
PSEL[4:0] --Priority Select Bits [4:0] Refer to 5 Resets and Interrupts.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 17
INIT --RAM and I/O Register Mapping
Bit 7 RAM3 RESET: 0 6 RAM2 0 5 RAM1 0 4 RAM0 0 3 REG3 0 2 REG2 0 1 REG1 0
$003D
Bit 0 REG0 0
Can be written only once in first 64 cycles out of reset in normal modes or at any time in special mode. RAM[3:0] --Internal RAM Map Position Specifies upper four bits of RAM address. At reset, RAM is mapped to $0000 along with register block. REG[3:0] --128-Byte Register Block Map Position Specifies upper four bits of register space address. At reset, registers are mapped to $0000. CONFIG --COP, ROM Mapping, EEPROM Enables
Bit 7 ROMAD RESET: -- 6 -- 1 5 CLKX -- 4 PAREN -- 3 NOSEC -- 2 NOCOP -- 1 ROMON --
$003F
Bit 0 EEON --
CONFIG is made up of EEPROM cells and static working latches. The operation of the MCU is controlled directly by these latches and not the actual EEPROM byte. When programming the CONFIG register, the EEPROM byte is being accessed. When the CONFIG register is being read, the static latches are being accessed. These bits can be read at any time. The value read is the one latched into the register from the EEPROM cells during the last reset sequence. A new value programmed into this register cannot be read until after a subsequent reset sequence. Unused bits always read as ones. If SMOD = 1, CONFIG bits can be written at any time. If SMOD = 0 CONFIG bits can only be written using the EEPROM programming sequence, and are neither readable nor active until latched via the next reset. ROMAD -- ROM/EPROM Mapping Control In single-chip mode ROMAD is forced to one out of reset. 0 = ROM/EPROM located at $2000-$7FFF ($2000-$9FFF in MC68HC11KA2) 1 = ROM/EPROM located at $A000-$FFFF ($8000-$FFFF in MC68HC11KA2) Bit 6 -- Not implemented Always reads one CLKX -- XOUT Clock Enable 0 = XOUT pin disabled 1 = x clock driven out on the XOUT pin PAREN -- Pull-Up Assignment Register Enable Refer to 6 Parallel Input/Output. NOSEC -- Security Disable NOSEC is invalid unless the security mask option is specified before the MCU is manufactured. If security mask option is omitted NOSEC always reads one. 0 = Security enabled 1 = Security disabled
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MC68HC11KA4 MC68HC11KA4TS/D
NOCOP -- COP System Disable Resets to programmed value 0 = COP enabled (forces reset on time-out) 1 = COP disabled (does not force reset on time-out) ROMON -- ROM/EPROM Enable In single-chip mode, ROMON is forced to one out of reset. In special test mode, ROMON is forced to zero out of reset. 0 = ROM/EPROM removed from memory map 1 = ROM/EPROM present in memory map EEON -- EEPROM Enable 0 = EEPROM disabled from memory map 1 = EEPROM present in memory map with location depending on value specified in EE[3:0] in INIT2 OPT2 --System Configuration Options 2
Bit 7 -- RESET: 0 6 CWOM 0 5 -- 0 4 IRVNE -- 3 LSBF 0 2 SPR2 0 1 XDV1 0
$0038
Bit 0 XDV0 0
Bit 7 -- Not implemented Always reads zero CWOM -- Port C Wired-OR Mode Refer to 6 Parallel Input/Output. Bit 5 -- Not implemented Always reads zero IRVNE -- Internal Read Visibility/Not E Can be written at any time if SMOD = 1. If SMOD = 0, only one write is allowed. In expanded mode, IRVNE determines whether IRV is on or off. In special test mode, IRVNE is reset to one. In all other modes, IRVNE is reset to zero. 0 = No internal read visibility on external bus 1 = Data from internal reads is driven out of the external data bus. In single-chip modes, this bit determines whether the E clock drives out from the chip. 0 = E is driven out from the chip. 1 = E pin is driven low.
Mode Single Chip Expanded Boot Special Test IRVNE Out of Reset 0 0 0 1 E Clock Out of Reset On On On On IRV Out of Reset Off Off Off On IRVNE Affects Only E IRV E IRV IRVNE Can Be Written Once Once Once Once
LSBF -- SPI LSB First Enable Refer to 8 Serial Peripheral Interface. SPR2 -- SPI Clock Rate Select Refer to 8 Serial Peripheral Interface.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 19
XDV[1:0] -- XOUT Clock Divide Select These two bits control the frequency of the clock that is driven out the XOUT pin. The CLKX bit in the CONFIG register controls whether this clock is on or off. When a clock rate is selected, allow a maximum of 16 cycles for stabilization. During reset a frequency of EXTAL is output. This frequency can be divided after reset. Note that the phase relationship between the 4XDV1 signal and both EXTAL and E cannot be predicted. Refer to the following table for further information about XOUT frequencies. Table 5 XOUT Frequencies
XDV[1:0] 0 0 1 1 XDV[1:0] 0 0 1 1 0 1 0 1 0 1 0 1 EXTAL Divided By 1 4 6 8 EXTAL Divided By 1 4 6 8 Frequency at EXTAL = 8 MHz 8 MHz 2 MHz 1.33 MHz 1 MHz Frequency at EXTAL = 8.4 MHz 8.4 MHz 2.1 MHz 1.4 MHz 1.05 MHz Frequency at EXTAL = 12 MHz 12 MHz 3 MHz 2 MHz 1.5 MHz Frequency at EXTAL = 12.6 MHz 12.6 MHz 3.15 MHz 2.1 MHz 1.57 MHz Frequency at EXTAL = 16 MHz 16 MHz 4 MHz 2.7 MHz 2 MHz Frequency at EXTAL = 16.8 MHz 16.8 MHz 4.2 MHz 2.8 MHz 2.1 MHz
NOTE The XOUT pin is not bonded in the 64-pin package.
MOTOROLA 20
MC68HC11KA4 MC68HC11KA4TS/D
3 Erasable Programmable Read-Only Memory
The MC68HC711KA4 has 24 Kbytes of ROM/EPROM. The MC68HC711KA2 has 32 Kbytes of ROM/ EPROM. In all parts, the ROM/EPROM can be mapped to one of two locations in the memory map. The locations are as follows: In the MC68HC11KA4, the ROM/EPROM can be mapped at $2000-$7FFF or $A000-$FFFF. If it is mapped to $A000-$FFFF, vector space is included. In single-chip mode the MC68HC11KA4 ROM/ EPROM is forced to $A000-$FFFF (ROMAD = 1) and enabled (ROMON = 1), regardless of the value in the CONFIG register. In the MC68HC11KA2, the ROM/EPROM can be mapped at $0000-$7FFF or $8000-$FFFF. If it is mapped to $8000-$FFFF, vector space is included. In single-chip mode the MC68HC11KA2 ROM/ EPROM is forced to $8000-$FFFF (ROMAD = 1) and enabled (ROMON = 1), regardless of the value in the CONFIG register. In PROG mode, the EPROM/OTPROM is programmed as a stand-alone EPROM by adapting the MCU footprint to the 27256-type EPROM and using an appropriate EPROM programmer. Programming EPROM/OTPROM requires an external 12.25 volt nominal power supply (VPPE). There are two methods that can be used to program and verify EPROM/OTPROM. In normal MCU mode, EPROM/OTPROM can be programmed in any operating mode --special test, bootstrap, expanded, or single chip. Normal programming is completed using the EPROG register. To program the EPROM, complete the following steps using the EPROG register: 1. 2. 3. 4. 5. 6. Write to EPROG with the ELAT bit set. Write data to the desired address. Write to EPROG with the ELAT and EPGM bits set. Delay for 10 ms or more, as appropriate. Clear the EPGM bit in EPROG to turn off the VPPE voltage. Clear the EPROG register to reconfigure the EPROM address and data buses for normal operation. $002B
4 EXCOL 0 3 EXROW 0 2 -- 0 1 -- 0 Bit 0 EPGM 0
EPROG --EPROM Programming Control
Bit 7 MBE RESET: 0 6 -- 0 5 ELAT 0
MBE -- Multiple Byte Program Enable Used for factory test purposes only Bit 6 -- Not implemented Always reads zero ELAT -- EPROM Latch Control If ELAT = 1, EPROM is in programming mode and cannot be read. If ELAT = 1, writes to EPROM cause address and data to be latched. 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming EXCOL -- Select Extra Columns Used for factory test purposes only EXROW -- Select Extra Row Used for factory test purposes only Bits [2:1] -- Not implemented Always read zero
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 21
EPGM -- EPROM Program Command If ELAT = 1 then EPGM = 0. 0 = Programming power to EPROM array switched off 1 = Power to EPROM array switched on
EPROM MODE PIN CONNECTIONS MCU PIN FUNCTIONS EPROM PIN FUNCTIONS
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14
PF0/ADDR0 PF1/ADDR1 PF2/ADDR2 PF3/ADDR3 PF4/ADDR4 PF5/ADDR5 PF6/ADDR6 PF7/ADDR7 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB3/ADDR11 PB4/ADDR12 PB5/ADDR13 PB6/ADDR14
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 INTERNAL ADDR6 24 KBYTE ADDR7 ADDR8 (32 KBYTES, KA2) EPROM ADDR9 ADDR10 27256 ADDR11 FOOTPRINT ADDR12 ADDR13 ADDR14
O0 O1 O2 O3 O4 O5 O6 O7 OE CE VPP VCC VSS
PC0/DATA0 PC1/DATA1 PC2/DATA2 PC3/DATA3 PC4/DATA4 PC5/DATA5 PC6/DATA6 PC7/DATA7 PB7/ADDR15 IRQ XIRQ/VPPE VDD VSS PE0/AN0 PE1/AN1 PE2/AN2 PE3/AN3 PE4/AN4 PE5/AN5 PE6/AN6 PE7/AN7 PH0/PW1 PH1/PW2 PH2/PW3 PH3/PW4
O0 O1 O2 O3 O4 O5 O6 O7 OE CE VPP VCC VSS
UNUSED INPUTS
NOTE 2
NOTE 4
GND GND GND
PA0/IC3 PA1/IC2 PA2/IC1
MC68HC711KA4 MC68HC711KA2
GND GND GND GND GND
PA3/IC4/OC5/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1
GND GND GND GND NOTE 1
VRL VRH EXTAL NOTE 1 GND GND GND GND GND GND GND PG7/R/W PD0/RxD PD1/TxD PD2/MISO PD3/MOSI PD4/SCK PD5/SS
GND GND GND
XTAL UNUSED XOUT OUTPUTS E TESTxx (3) MODA/LIR MODB/VSTBY RESET GND GND GND
NOTE 3
NOTE 4
NOTES: 1. Unused Inputs - grounding is recommended. 2. Unused Inputs - these pins may be left unterminated. 3. Unused Outputs - these pins should be left unconnected. 4. Grounding these six pins configures the MC68HC711KA4/KA2 for EPROM emulation mode.
Figure 8 Wiring Diagram for MC68HC711KA4/KA2 EPROM in PROG Mode
MOTOROLA 22
MC68HC11KA4 MC68HC11KA4TS/D
4 Electrically Erasable Programmable Read-Only Memory
The 640-byte on-chip EEPROM is initially located from $0D80 to $0FFF after reset in all modes. It can be mapped to any other 4 Kbyte boundary by writing to the INIT2 register. The EEPROM is enabled by the EEON bit in the CONFIG register. Programming and erasing is controlled by the PPROG register. An internal oscillator clock-run charge pump supplies the programming voltage. Use of the block protect register (BPROT) prevents inadvertent writes to (or erases of) blocks of EEPROM. The CSEL bit in the OPTION register selects the on-chip oscillator clock for programming and erasing while operating at frequencies below 1 MHz. Refer to 5 Resets and Interrupts. In special mode there is an extra row of 16 bytes of EEPROM (located at $0D60), which is used for factory testing. Endurance and data retention specifications do not apply to this row. The erased state of EEPROM is $FF (all ones). To erase the EEPROM, ensure that the proper bits of the BPROT register are cleared, then complete the following steps using the PPROG register: 1. Write to PPROG with the ERASE, EELAT, and appropriate BYTE and ROW bits set. 2. Write to the appropriate EEPROM address with any data. Row erase only requires a write to any location in the row. Bulk erase is accomplished by writing to any location in the array. 3. Write to PPROG with ERASE, EELAT, EEPGM, and the appropriate BYTE and ROW bits set. 4. Delay for 10 ms or more, as appropriate. 5. Clear the EEPGM bit in PPROG to turn off the high voltage. 6. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal operation. To program the EEPROM, ensure the proper bits of the BPROT register are cleared, then complete the following steps using the PPROG register: 1. 2. 3. 4. 5. 6. Write to PPROG with the EELAT bit set. Write data to the desired address. Write to PPROG with the EELAT and EEPGM bits set. Delay for 10 ms or more, as appropriate. Clear the EEPGM bit in PPROG to turn off the high voltage. Clear the PPROG register to reconfigure the EEPROM address and data buses for normal operation. CAUTION Since it is possible to perform other operations while the EEPROM programming/ erase operation is in progress, it is fairly common to start the operation then return to the main program until the 10 ms is completed. When the EELAT bit is set at the beginning of a program/erase operation, the EEPROM is electronically removed from the memory map; thus, it is not accessible during the program/erase cycle. Care must be taken to ensure that EEPROM resources will not be needed by any routines in the code during the 10 ms program/erase time.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 23
BPROT --Block Protect
Bit 7 BULKP RESET: 1 6 LVPEN 1 5 BPRT4 1 4 PTCON 1 3 BPRT3 1 2 BPRT2 1 1 BPRT1 1
$0035
Bit 0 BPRT0 1
NOTE Block protect register bits can be written to zero (protection disabled) only once within 64 cycles of a reset in normal modes, or at any time in special mode. Block protect register bits can be written to one (protection enabled) at any time. BULKP -- Bulk Erase of EEPROM Protect 0 = EEPROM can be bulk erased normally 1 = EEPROM cannot be bulk or row erased LVPEN -- Low Voltage Programming Protect Enable If LVPEN = 1, programming of the EEPROM is enabled unless the LVPI circuit detects that VDD has fallen below a safe operating voltage thus setting the low voltage programming inhibit bit in PPROG register (LVPI = 1). 0 = Low voltage programming protect for EEPROM disabled 1 = Low voltage programming protect for EEPROM enabled BPRT[4:0] --Block Protect Bits for EEPROM 0 = Protection disabled 1 = Protection enabled
Bit Name BPRT4 BPRT3 BPRT2 BPRT1 BPRT0 Block Protected $xF80-$xFFF $xE60-$xF7F $xDE0-$xE5F $xDA0-$xDDF $xD80-$xD9F Block Size 128 Bytes 288 Bytes 128 Bytes 64 Bytes 32 Bytes
PTCON -- Protect for CONFIG 0 = CONFIG register can be programmed or erased normally 1 = CONFIG register cannot be programmed or erased INIT2 --EEPROM Mapping
Bit 7 EE3 RESET: 0 6 EE2 0 5 EE1 0 4 EE0 0 3 -- 0 2 -- 0 1 -- 0
$0037
Bit 0 -- 0
INIT2 can be written only once in normal modes, any time in special modes. EE[3:0] -- EEPROM Map Position EEPROM is at $xD80-$xFFF, where x is the hexadecimal digit represented by EE[3:0] bits. Bits [3:0] -- Not implemented Always read zero
MOTOROLA 24
MC68HC11KA4 MC68HC11KA4TS/D
PPROG -- EEPROM Programming Control
Bit 7 ODD RESET: 0 6 EVEN 0 5 LVPI 0 4 BYTE 0 3 ROW 0 2 ERASE 0 1 EELAT 0
$003B
Bit 0 EEPGM 0
ODD -- Program Odd Rows in Half of EEPROM (TEST) EVEN -- Program Even Rows in Half of EEPROM (TEST) LVPI -- Low Voltage Programming Inhibit LVPI can be read at any time and writes to LVPI have no meaning nor effect. LVPI is set if LVPEN bit in BPROT register equals 1 and the LVPI circuit detects that VDD has fallen below a safe operating voltage. Once set, LVPI is cleared when VDD returns to a safe operating voltage or if LVPEN bit in BPROT register is cleared. If LVPEN = 0, then LVPI is always zero and has no meaning nor effect. 0 = EEPROM programming enabled 1 = EEPROM programming disabled BYTE -- Byte/Other EEPROM Erase Mode 0 = Row or bulk erase mode used 1 = Erase only one byte of EEPROM ROW -- Row/All EEPROM Erase Mode (only valid when BYTE = 0) 0 = All 640 bytes of EEPROM erased 1 = Erase only one 16-byte row of EEPROM
BYTE 0 0 1 1 ROW 0 1 0 1 Action Bulk Erase (All 640 Bytes) Row Erase (16 Bytes) Byte Erase Byte Erase
ERASE -- Erase/Normal Control for EEPROM 0 = Normal read or program mode 1 = Erase mode EELAT -- EEPROM Latch Control 0 = EEPROM address and data bus configured for normal reads 1 = EEPROM address and data bus configured for programming or erasing EEPGM -- EEPROM Program Command 0 = Program or erase voltage switched off to EEPROM array 1 = Program or erase voltage switched on to EEPROM array Refer also to INIT2 register.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 25
5 Resets and Interrupts
The MC68HC11KA4/KA2 has three reset vectors and 18 interrupt vectors. The reset vectors are as follows: * RESET, or Power-On Reset * Clock Monitor Fail * COP Failure The 18 interrupt vectors service 22 interrupt sources (three non-maskable, 19 maskable). The three nonmaskable interrupt vectors are as follows: * XIRQ Pin (X-Bit Interrupt) * Illegal Opcode Trap * Software Interrupt On-chip peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized according to a default arrangement; however, any one source can be elevated to the highest maskable priority position by a software-accessible control register (HPRIO). The HPRIO register can be written at any time, provided bit I in the CCR is set. Nineteen interrupt sources in the MC68HC11KA4/KA2 are subject to masking by the global interrupt mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the external interrupt (IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in the M68HC11 have separate interrupt vectors; therefore, there is usually no need for software to poll control registers to determine the cause of an interrupt. For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system is cleared by the automatic clearing mechanism consisting of a read of the SCI status register while RDRF is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request would be to read the SCI status register to check for receive errors, then to read the received data from the SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any special instructions. Refer to the following table for a list of interrupt and reset vector assignments
MOTOROLA 26
MC68HC11KA4 MC68HC11KA4TS/D
Vector Address FFC0, C1 - FFD4, D5 FFD6, D7 Reserved
Interrupt Source
CCR Mask Bit -- I
Local Mask -- RIE RIE TIE TCIE ILIE
SCI Serial System * SCI Receive Data Register Full * SCI Receiver Overrun * SCI Transmit Data Register Empty * SCI Transmit Complete * SCI Idle Line Detect
FFD8, D9 FFDA, DB FFDC, DD FFDE, DF FFE0, E1 FFE2, E3 FFE4, E5 FFE6, E7 FFE8, E9 FFEA, EB FFEC, ED FFEE, EF FFF0, F1 FFF2, F3 FFF4, F5 FFF6, F7 FFF8, F9 FFFA, FB FFFC, FD FFFE, FF
SPI Serial Transfer Complete Pulse Accumulator Input Edge Pulse Accumulator Overflow Timer Overflow Timer Input Capture 4/Output Compare 5 Timer Output Compare 4 Timer Output Compare 3 Timer Output Compare 2 Timer Output Compare 1 Timer Input Capture 3 Timer Input Capture 2 Timer Input Capture 1 Real-Time Interrupt IRQ XIRQ Pin Software Interrupt Illegal Opcode Trap COP Failure Clock Monitor Fail RESET
I I I I I I I I I I I I I I X None None None None None
SPIE PAII PAOVI TOI I4/O5I OC4I OC3I OC2I OC1I IC3I IC2I IC1I RTII None None None None NOCOP CME None
OPTION --System Configuration Options
Bit 7 ADPU RESET: 0 6 CSEL 0 5 IRQE* 0 4 DLY 1 3 CME 0 2 FCME* 0 1 CR1* 0
$0039
Bit 0 CR0* 0
*Can be written only once in first 64 cycles out of reset in normal mode, or at any time in special mode.
ADPU --A/D Converter Power-Up Refer to 9 Analog-to-Digital Converter. CSEL --Clock Select Refer to 9 Analog-to-Digital Converter. IRQE --IRQ Select Edge Sensitive Only 0 = Low level recognition 1 = Falling edge recognition
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 27
DLY --Enable Oscillator Start-Up Delay on Exit from STOP 0 = No stabilization delay on exit from STOP 1 = Stabilization delay enabled on exit from STOP CME -- Clock Monitor Enable 0 = Clock monitor disabled; slow clocks can be used 1 = Slow or stopped clocks cause clock failure reset FCME -- Force Clock Monitor Enable 0 = Clock monitor follows the state of the CME bit 1 = Clock monitor circuit is enabled until next reset CR[1:0] -- COP Timer Rate Select Table 6 COP Timer Rate Select
CR[1:0] Divide E/215 By 1 4 16 64 E= XTAL = 8.0 MHz Time-out -0/+16.4 ms 16.384 ms 65.536 ms 262.14 ms 1.049 s 2.0 MHz XTAL = 12.0 MHz Time-out -0/+10.9 ms 10.923 ms 43.691 ms 174.76 ms 699.05 ms 3.0 MHz XTAL = 16.0 MHz Time-out -0/+8.2 ms 8.192 ms 32.768 ms 131.07 ms 524.29 ms 4.0 MHz
000 001 010 011
COPRST -- Arm/Reset COP Timer Circuitry
Bit 7 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0
$003A
Bit 0 0 0
Write $55 to COPRST to arm COP watchdog clearing mechanism. Write $AA to COPRST to reset COP watchdog. HPRIO -- Highest Priority I-Bit Interrupt and Miscellaneous
Bit 7 RBOOT* RESET: -- 6 SMOD* -- 5 MDA* -- 4 PSEL4 0 3 PSEL3 0 2 PSEL2 1 1 PSEL1 1
$003C
Bit 0 PSEL0 0
*RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode.
RBOOT -- Read Bootstrap ROM Refer to 2 Operating Modes and On-Chip Memory. SMOD -- Special Mode Select Refer to 2 Operating Modes and On-Chip Memory. MDA -- Mode Select A Refer to 2 Operating Modes and On-Chip Memory.
MOTOROLA 28
MC68HC11KA4 MC68HC11KA4TS/D
PSEL[4:0] -- Priority Select Bits [4:0] Can be written only while bit I in the CCR is set (interrupts disabled). These bits select one interrupt source to be elevated above all other I-bit related sources.
PSELx 4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X 1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X Interrupt Source Promoted Reserved (Default to IRQ) Reserved (Default to IRQ) Reserved (Default to IRQ) IRQ Real-Time Interrupt Timer Input Capture 1 Timer Input Capture 2 Timer Input Capture 3 Timer Output Compare 1 Timer Output Compare 2 Timer Output Compare 3 Timer Output Compare 4 Timer Input Capture 4/Output Compare 5 Timer Overflow Pulse Accumulator Overflow Pulse Accumulator Input Edge SPI Serial Transfer Complete SCI Serial System Reserved (Default to IRQ) Reserved (Default to IRQ) Reserved (Default to IRQ) Reserved (Default to IRQ)
CONFIG -- COP, ROM Mapping, EEPROM Enables
Bit 7 ROMAD RESET: -- 6 -- 1 5 CLKX -- 4 PAREN -- 3 NOSEC -- 2 NOCOP -- 1 ROMON --
$003F
Bit 0 EEON --
CONFIG is made up of EEPROM cells and static latches. The operation of the MCU is controlled directly by these latches and not the actual EEPROM byte. When programming the CONFIG register, the EEPROM byte is being accessed. When the CONFIG register is being read, the static latches are being accessed. These bits can be read at any time. The value read is the one latched into the register from the EEPROM cells during the last reset sequence. A new value programmed into this register cannot be read until after a subsequent reset sequence. Unused bits always read as ones. If SMOD = 1, CONFIG bits can be written at any time. If SMOD = 0 CONFIG bits can only be written using the EEPROM programming sequence, and are neither readable nor active until latched via the next reset. ROMAD -- ROM/EPROM Mapping Control Refer to 2 Operating Modes and On-Chip Memory.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 29
Bit 6 -- Not implemented Always reads one CLKX -- XOUT Clock Refer to 2 Operating Modes and On-Chip Memory. PAREN -- Pull-Up Assignment Register Enable Refer to 6 Parallel Input/Output. NOSEC -- Security Disable Refer to 2 Operating Modes and On-Chip Memory. NOCOP -- COP System Disable Resets to programmed value 0 = COP enabled (forces reset on time-out) 1 = COP disabled (does not force reset on time-out) ROMON -- ROM/EPROM Enable Refer to 2 Operating Modes and On-Chip Memory. EEON -- EEPROM Enable Refer to 2 Operating Modes and On-Chip Memory.
MOTOROLA 30
MC68HC11KA4 MC68HC11KA4TS/D
6 Parallel Input/Output
The MC68HC11KA4/KA2 has up to 51 input/output lines, depending on the operating mode. To enhance the I/O functions, the data bus of this microcontroller is non-multiplexed. The following table is a summary of the configuration and features of each port.
Port Port A Port B Port C Port D Port E Port F Port G Port H
Input Pins -- -- -- -- 8* -- -- --
Output Pins -- -- -- -- -- -- -- --
Bidirectional Pins 8 8 8 6 -- 8 1 4 Timer
Shared Functions High Order Address Data Bus SCI and SPI A/D Converter Low Order Address R/W Signal PWMs
* Only four pins on 64-pin version.
CONFIG -- COP, ROM Mapping, EEPROM Enables
Bit 7 ROMAD RESET: -- 6 -- 1 5 CLKX -- 4 PAREN -- 3 NOSEC -- 2 NOCOP -- 1 ROMON --
$003F
Bit 0 EEON --
ROMAD -- ROM Mapping Control Refer to 2 Operating Modes and On-Chip Memory. Bit 6 -- Not implemented Always reads one CLKX -- XOUT Clock Enable Refer to 2 Operating Modes and On-Chip Memory. PAREN -- Pull-Up Assignment Register Enable 0 = Pull-ups always disabled regardless of state of bits in PPAR 1 = Pull-ups either enabled or disabled through PPAR NOSEC -- Security Disable Refer to 2 Operating Modes and On-Chip Memory. NOCOP -- COP System Disable Refer to 5 Resets and Interrupts. ROMON -- ROM/EPROM Enable Refer to 2 Operating Modes and On-Chip Memory. EEON -- EEPROM Enable Refer to 2 Operating Modes and On-Chip Memory.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 31
OPT2 --System Configuration Options 2
Bit 7 LIRDV RESET: 0 6 CWOM 0 5 -- 0 4 IRVNE -- 3 LSBF 0 2 SPR2 0 1 XDV1 0
$0038
Bit 0 XDV0 0
LIRDV -- LIR Driven Refer to 2 Operating Modes and On-Chip Memory. CWOM -- Port C Wired-OR Mode 0 = Port C operates normally. 1 = Port C outputs are open-drain. Bit 5 -- Not implemented Always reads zero IRVNE -- Internal Read Visibility/Not E Refer to 2 Operating Modes and On-Chip Memory. LSBF -- SPI LSB First Enable Refer to 8 Serial Peripheral Interface. SPR2 -- SPI Clock (SCK) Rate Select Refer to 8 Serial Peripheral Interface. XDV1, XDV0 -- XOUT Clock Divide Select Refer to 2 Operating Modes and On-Chip Memory. NOTE Do not confuse pin function with the electrical state of the pin at reset. All generalpurpose I/O pins configured as inputs at reset are in a high-impedance state and the contents of port data registers is undefined. In port descriptions, a "U" indicates this condition. The pin function is mode dependent. PORTA --Port A Data
Bit 7 PA7 RESET: Alt. Pin Func.: And/or: U PAI OC1 6 PA6 U OC2 OC1 5 PA5 U OC3 OC1 4 PA4 U OC4 OC1 3 PA3 U IC4/OC5 OC1 2 PA2 U IC1 -- 1 PA1 U IC2 --
$0000
Bit 0 PA0 U IC3 --
NOTE To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL register. Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled, writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4. PA7 drives the pulse accumulator input but also can be configured for general-purpose I/O, or output compare. Note that even when PA7 is configured as an output, the pin still drives the pulse accumulator input.
MOTOROLA 32
MC68HC11KA4 MC68HC11KA4TS/D
DDRA -- Data Direction Register for Port A
Bit 7 DDA7 RESET: 0 6 DDA6 0 5 DDA5 0 4 DDA4 0 3 DDA3 0 2 DDA2 0 1 DDA1 0
$0001
Bit 0 DDA0 0
DDA[7:0] --Data Direction for Port A 0 = Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output PORTB --Port B Data
Bit 7 PB7 S. Chip or Boot: RESET: Expan. or Test: PB7 U ADDR15 6 PB6 PB6 U ADDR14 5 PB5 PB5 U ADDR13 4 PB4 PB4 U ADDR12 3 PB3 PB3 U ADDR11 2 PB2 PB2 U ADDR10 1 PB1 PB1 U ADDR9
$0004
Bit 0 PB0 PB0 U ADDR8
Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are high impedance inputs with selectable internal pull-up resistors. In expanded or test modes, port B pins are high order address outputs and PORTB is not in the memory map. DDRB -- Data Direction Register for Port B
Bit 7 DDB7 RESET: 0 6 DDB6 0 5 DDB5 0 4 DDB4 0 3 DDB3 0 2 DDB2 0 1 DDB1 0
$0002
Bit 0 DDB0 0
DDB[7:0] -- Data Direction for Port B 0 = Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output PORTF -- Port F Data
Bit 7 PF7 S. Chip or Boot: RESET: Expan. or Test: PF7 U ADDR7 6 PF6 PF6 U ADDR6 5 PF5 PF5 U ADDR5 4 PF4 PF4 U ADDR4 3 PF3 PF3 U ADDR3 2 PF2 PF2 U ADDR2 1 PF1 PF1 U ADDR1
$0005
Bit 0 PF0 PF0 U ADDR0
Reset state is mode dependent. In single-chip or bootstrap modes, port F pins are high-impedance inputs with selectable internal pull-up resistors. In expanded or test modes, port F pins are low order address outputs and PORTF is not in the memory map.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 33
DDRF --Data Direction Register for Port F
Bit 7 DDF7 RESET: 0 6 DDF6 0 5 DDF5 0 4 DDF4 0 3 DDF3 0 2 DDF2 0 1 DDF1 0
$0003
Bit 0 DDF0 0
DDF[7:0] -- Data Direction for Port F 0 = Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output PORTC --Port C Data
Bit 7 PC7 S. Chip or Boot: RESET: Expan. or Test: PC7 0 DATA7 6 PC6 PC6 0 DATA6 5 PC5 PC5 0 DATA5 4 PC4 PC4 0 DATA4 3 PC3 PC3 0 DATA3 2 PC2 PC2 0 DATA2 1 PC1 PC1 0 DATA1
$0006
Bit 0 PC0 PC0 0 DATA0
Reset state is mode dependent. In single-chip or bootstrap modes, port C pins are high-impedance inputs. It is customary to have an external pull-up resistor on lines that are driven by open-drain devices. In expanded or test modes, port C pins are data bus inputs and outputs and PORTC is not in the memory map. DDRC -- Data Direction Register for Port C
Bit 7 DDC7 RESET: 0 6 DDC6 0 5 DDC5 0 4 DDC4 0 3 DDC3 0 2 DDC2 0 1 DDC1 0
$0007
Bit 0 DDC0 0
DDC[7:0] -- Data Direction for Port C 0 = Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output PORTD -- Port D Data
Bit 7 0 RESET: Alt. Pin Func.: 0 -- 6 0 0 -- 5 PD5 U SS 4 PD4 U SCK 3 PD3 U MOSI 2 PD2 U MISO 1 PD1 U TxD
$0008
Bit 0 PD0 U RxD
MOTOROLA 34
MC68HC11KA4 MC68HC11KA4TS/D
DDRD -- Data Direction Register for Port D
Bit 7 -- RESET: 0 6 -- 0 5 DDD5 0 4 DDD4 0 3 DDD3 0 2 DDD2 0 1 DDD1 0
$0009
Bit 0 DDD0 0
Bits [7:6] --Not implemented Always read zero DDD[5:0] -- Data Direction for Port D 0 = Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output NOTE When the SPI system is in slave mode, DDD5 has no meaning nor effect. When the SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an error detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI system is enabled and expects any of bits [4:2] to be an input that bit will be an input regardless of the state of the associated DDR bit. If any of bits [4:2] are expected to be outputs that bit will be an output only if the associated DDR bit is set. PORTE -- Port E Data
Bit 7 PE7* RESET: Alt. Pin Func.: U AN7 6 PE6* U AN6 5 PE5* U AN5 4 PE4* U AN4 3 PE3 U AN3 2 PE2 U AN2 1 PE1 U AN1
$000A
Bit 0 PE0 U AN0
*Not bonded on 64-pin version.
PPAR --Port Pull-Up Assignment
Bit 7 -- RESET: 0 6 -- 0 5 -- 0 4 -- 0 3 HPPUE 1 2 GPPUE 1 1 FPPUE 1
$002C
Bit 0 BPPUE 1
Bits [7:4] -- Not implemented Always read zero xPPUE -- Port x Pin Pull-Up Enable Refer to PAREN bit in CONFIG register discussed in 6 Parallel Input/Output. 0 = Port x pin on-chip pull-up devices disabled 1 = Port x pin on-chip pull-up devices enabled NOTE FPPUE and BPPUE do not apply in expanded mode because ports F and B are address outputs.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 35
PORTH -- Port H Data
Bit 7 -- RESET: Alt. Pin Func.: 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 PH3 U PW4 2 PH2 U PW3 1 PH1 U PW2
$007C
Bit 0 PH0 U PW1
Port H pins reset to high-impedance inputs with selectable internal pull-up resistors. DDRH -- Data Direction Register for Port H
Bit 7 -- RESET: 0 6 -- 0 5 -- 0 4 -- 0 3 DDH3 1 2 DDH2 1 1 DDH1 1
$007D
Bit 0 DDH0 1
Bits [7:4] -- Not implemented Always read zero DDH[3:0] -- Data Direction for Port H 0 = Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output NOTE In any mode, PWM circuitry forces the I/O state to be an output for each port H line associated with an enabled pulse-width modulator channel. In these cases, data direction bits are not changed and have no effect on these lines. DDRH reverts to controlling the I/O state of a pin when the associated function is disabled. Refer to 12 Pulse-Width Modulation Timer for further information. PORTG -- Port G Data
Bit 7 PG7 RESET: Alt. Pin Func.: U R/W 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 -- 0 -- 1 -- 0 --
$007E
Bit 0 -- 0 --
Port G pins reset to high-impedance inputs with selectable internal pull-up resistors. In expanded and special test modes PG7 becomes R/W. DDRG -- Data Direction Register for Port G
Bit 7 DDG7 RESET: 0 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0
$007F
Bit 0 -- 0
DDG7 -- Data Direction for Port G 0 = Bit set to zero to configure corresponding I/O pin for input only 1 = Bit set to one to configure corresponding I/O pin for output In expanded and test modes, bit 7 is configured for R/W, forcing the state of this pin to be an output although the DDRG value remains zero. Bits [6:0] -- Not implemented Always read zero
MOTOROLA 36
MC68HC11KA4 MC68HC11KA4TS/D
7 Serial Communications Interface
The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one of two independent serial I/O subsystems in the MC68HC11KA4/KA2. Rearranging registers and control bits used in previous M68HC11 family devices has enhanced the existing SCI system and added new features, which include the following: * A 13-bit modulus prescaler that allows greater baud rate control * A new idle mode detect, independent of preceding serial data * A receiver active flag * Hardware parity for both transmitter and receiver The enhanced baud rate generator is shown in the following diagram. Refer to the table of SCI baud rate control values for standard values.
EXTAL
XTAL
OSCILLATOR AND CLOCK GENERATOR (/4)
INTERNAL BUS CLOCK (PH2)
/3
0:0 0:1
/4
1:0
/13
SCP[1:0] 1:1
E AS
SCR[2:0] 0:0:0
/2 /2 /2 /2 /2 /2 /2
0:0:1
0:1:0
0:1:1
/16
1:0:0 SCI TRANSMIT BAUD RATE (1X)
1:0:1
1:1:0
1:1:1
SCI RECEIVE BAUD RATE (16X)
SCI BAUD GENERATOR
Figure 9 SCI Baud Generator Circuit Diagram
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 37
TRANSMITTER BAUD RATE CLOCK
SCDR Tx BUFFER
(WRITE-ONLY) DDD1
10 (11) - BIT Tx SHIFT REGISTER H (8) 7 6 5 4 3 2 1 0 L PIN BUFFER AND CONTROL PD1/ TxD
SHIFT ENABLE
JAM ENABLE
TRANSFER Tx BUFFER
PARITY GENERATOR
PREAMBLE--JAM 1's
BREAK--JAM 0's
SIZE 8/9
TRANSMITTER CONTROL LOGIC
FORCE PIN DIRECTION (OUT)
M WAKE ILT PE PT
SCCR1 SCI CONTROL 1
TDRE TIE TC TCIE TIE TCIE RIE ILIE TE RE RWU SBK SCCR2 SCI CONTROL 2 SCI Rx REQUESTS SCI INTERRUPT REQUEST
TDRE TC RDRF IDLE OR NF FE SCSR INTERRUPT STATUS
R8
INTERNAL DATA BUS
Figure 10 SCI Transmitter Block Diagram
MOTOROLA 38
MC68HC11KA4 MC68HC11KA4TS/D
RECEIVER BAUD RATE CLOCK DDD0 10 (11) - BIT Rx SHIFT REGISTER (8) 7 6 5 4 3 2 1 0 ALL ONES START (READ-ONLY) INTERNAL DATA BUS STOP /16 PD0/ RxD PIN BUFFER AND CONTROL DISABLE DRIVER RE RAF DATA RECOVERY
MSB
SCSR2 SCI STATUS 2
PARITY DETECT M
WAKE-UP LOGIC
RWU
LOOPS WOMS
M WAKE ILT PE PT
SCCR1 SCI CONTROL 1
TDRE TC RDRF IDLE OR NF FE PF SCSR1 SCI STATUS 1
SCDR Rx BUFFER
RDRF RIE IDLE ILIE OR RIE TIE TCIE RIE ILIE TE RE RWU SBK SCCR2 SCI CONTROL 2 SCI Tx REQUESTS SCI INTERRUPT REQUEST
Figure 11 SCI Receiver Block Diagram
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 39
SCBDH/L --SCI Baud Rate Control High/Low
Bit 7 $0070 RESET: $0071 RESET: BTST 0 SBR7 0 6 BSPL 0 SBR6 0 5 -- 0 SBR5 0 4 SBR12 0 SBR4 0 3 SBR11 0 SBR3 0 2 SBR10 0 SBR2 1 1 SBR9 0 SBR1 0
$0070, $0071
Bit 0 SBR8 0 SBR0 0 Low High
BTST -- Baud Register Test (TEST) BSPL -- Baud Rate Counter Split (TEST) Bit 5 -- Not implemented Always reads zero SBR[12:0] -- SCI Baud Rate Selects Use the following formula to calculate SCI baud rate. Refer to the table of baud rate control values for example rates: SCI baud rate = EXTAL /[16 (2 BR)] Where BR is the contents of SCBDH, L (BR = 1, 2, 3, ..., 8191). BR = 0 disables the baud rate generator. Table 7 SCI Baud Rate Control Values
Target Baud Rate 110 150 300 600 1200 2400 4800 9600 19.2 K 38.4 K 2272 1666 833 416 208 104 52 26 13 -- 8 MHz Dec Value Hex Value $08E0 $0682 $0341 $01A0 $00D0 $0068 $0034 $001A $000D -- 3409 2500 1250 625 312 156 78 39 20 -- Crystal Frequency (EXTAL) 12 MHz Dec Value Hex Value $0D51 $09C4 $04E2 $0271 $0138 $009C $004E $0027 $0014 -- 4545 3333 1666 833 416 208 104 52 26 13 16 MHz Dec Value Hex Value $11C1 $0D05 $0682 $0341 $01A0 $00D0 $0068 $0034 $001A $000D
SCCR1 --SCI Control 1
Bit 7 LOOPS RESET: 0 6 WOMS 0 5 -- 0 4 M 0 3 WAKE 0 2 ILT 0 1 PE 0
$0072
Bit 0 PT 0
LOOPS -- SCI LOOP Mode Enable 0 = SCI transmit and receive operate normally 1 = SCI transmit and receive are disconnected from TxD and RxD pins, and transmitter output is fed back into the receiver input
MOTOROLA 40
MC68HC11KA4 MC68HC11KA4TS/D
WOMS -- Wired-OR Mode for SCI Pins (PD1, PD0; See also DWOM bit in SPCR.) 0 = TxD and RxD operate normally 1 = TxD and RxD are open drains if operating as an output Bit 5 -- Not implemented Always reads zero M -- Mode (Select Character Format) 0 = Start bit, 8 data bits, 1 stop bit 1 = Start bit, 9 data bits, 1 stop bit WAKE -- Wakeup by Address Mark/Idle 0 = Wakeup by IDLE line recognition 1 = Wakeup by address mark (most significant data bit set) ILT -- Idle Line Type 0 = Short (SCI counts consecutive ones after start bit) 1 = Long (SCI counts ones only after stop bit) PE -- Parity Enable 0 = Parity disabled 1 = Parity enabled PT -- Parity Type 0 = Parity even (even number of ones causes parity bit to be zero, odd number of ones causes parity bit to be one) 1 = Parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity bit to be one) SCCR2 --SCI Control 2
Bit 7 TIE RESET: 0 6 TCIE 0 5 RIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0
$0073
Bit 0 SBK 0
TIE -- Transmit Interrupt Enable 0 = TDRE interrupts disabled 1 = SCI interrupt requested when TDRE status flag is set TCIE -- Transmit Complete Interrupt Enable 0 = TC interrupts disabled 1 = SCI interrupt requested when TC status flag is set RIE -- Receiver Interrupt Enable 0 = RDRF and OR interrupts disabled 1 = SCI interrupt requested when RDRF flag or the OR status flag is set ILIE -- Idle Line Interrupt Enable 0 = IDLE interrupts disabled 1 = SCI interrupt requested when IDLE status flag is set TE -- Transmitter Enable 0 = Transmitter disabled 1 = Transmitter enabled
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 41
RE -- Receiver Enable 0 = Receiver disabled 1 = Receiver enabled RWU -- Receiver Wakeup Control 0 = Normal SCI receiver 1 = Wakeup enabled and receiver interrupts inhibited SBK -- Send Break 0 = Break generator off 1 = Break codes generated as long as SBK = 1 SCSR1 --SCI Status Register 1
Bit 7 TDRE RESET: 1 6 TC 1 5 RDRF 0 4 IDLE 0 3 OR 0 2 NF 0 1 FE 0
$0074
Bit 0 PF 0
TDRE -- Transmit Data Register Empty Flag This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR1 with TDRE set and then writing to SCDR. 0 = SCDR busy 1 = SCDR empty TC -- Transmit Complete Flag This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear the TC flag by reading SCSR1 with TC set and then writing to SCDR. 0 = Transmitter busy 1 = Transmitter idle RDRF -- Receive Data Register Full Flag Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. RDRF is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading SCSR1 with RDRF set and then reading SCDR. 0 = SCDR empty 1 = SCDR full IDLE -- Idle Line Detected Flag This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1 with IDLE set and then reading SCDR. 0 = RxD line is active 1 = RxD line is idle OR -- Overrun Error Flag OR is set if a new character is received before a previously received character is read from SCDR. Clear the OR flag by reading SCSR1 with OR set and then reading SCDR. 0 = No overrun 1 = Overrun detected NF -- Noise Error Flag NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR1 with NF set and then reading SCDR. 0 = Unanimous decision 1 = Noise detected
MOTOROLA 42
MC68HC11KA4 MC68HC11KA4TS/D
FE -- Framing Error FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR1 with FE set and then reading SCDR. 0 = Stop bit detected 1 = Zero detected PF -- Parity Error Flag PF is set if received data has incorrect parity. Clear PF by reading SCSR1 with PE set and then reading SCDR. 0 = Parity correct 1 = Incorrect parity detected SCSR2 --SCI Status Register 2
Bit 7 -- RESET: 0 6 -- 0 5 -- 0 4 -- 0 3 -- 0 2 -- 0 1 -- 0
$0075
Bit 0 RAF 0
Bits [7:1] -- Not implemented Always read zero RAF -- Receiver Active Flag (Read only) 0 = A character is not being received 1 = A character is being received SCDRH/L --SCI Data Register High/Low
Bit 7 $0076 $0077 R8 R7/T7 6 T8 R6/T6 5 -- R5/T5 4 -- R4/T4 3 -- R3/T3 2 -- R2/T2 1 -- R1/T1
$0076, $0077
Bit 0 -- R0/T0 SCDRH (High) SCDRL (Low)
R8 -- Receiver Bit 8 Ninth serial data bit received when SCI is configured for a nine data bit operation. T8 -- Transmitter Bit 8 Ninth serial data bit transmitted when SCI is configured for a nine data bit operation. Bits [5:0] -- Not implemented Always read zero R/T[7:0] -- Receiver/Transmitter Data Bits [7:0] SCI data is double buffered in both directions.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 43
8 Serial Peripheral Interface
The SPI allows the MCU to communicate synchronously with peripheral devices and other microprocessors. Data rates can be as high as 2 Mbits per second when configured as a master and 4 Mbits per second when configured as a slave (assuming 4 MHz bus speed). Two control bits in OPT2 allow the transfer of data either MSB or LSB first and select an additional divide by four stage to be inserted before the SPI baud rate clock divider.
INTERNAL MCU CLOCK
S M
MISO PD2
/2
8/16-BIT SHIFT REGISTER READ DATA BUFFER
CLOCK SPI CLOCK (MASTER) SELECT CLOCK LOGIC S M
PIN CONTROL LOGIC
DIVIDER /4 /16 /32
MSB
LSB
M S
MOSI PD3
SCK PD4
SPR1
SPR0
SS PD5 MSTR SPE DWOM MSTR SPE SPI CONTROL
SPIF WCOL
MODF
SPIE SPE DWOM
MSTR
CPOL CPHA
8 SPI STATUS REGISTER 8 8 SPI CONTROL REGISTER
SPI INTERRUPT REQUEST
INTERNAL DATA BUS
SPR1 SPR0
SPI BLOCK 2SPR
Figure 12 SPI Block Diagram
MOTOROLA 44
MC68HC11KA4 MC68HC11KA4TS/D
SPCR --Serial Peripheral Control Register
Bit 7 SPIE RESET: 0 6 SPE 0 5 DWOM 0 4 MSTR 0 3 CPOL 0 2 CPHA 1 1 SPR1 U
$0028
Bit 0 SPR0 U
SPIE -- Serial Peripheral Interrupt Enable 0 = SPI interrupts disabled 1 = SPI interrupts enabled SPE -- Serial Peripheral System Enable 0 = SPI off 1 = SPI on DWOM -- Port D Wired-OR Mode Option for SPI Pins PD[5:2] (See also WOMS bit in SCCR1.) 0 = Normal CMOS outputs 1 = Open-drain outputs MSTR -- Master Mode Select 0 = Slave mode 1 = Master mode CPOL, CPHA -- Clock Polarity, Clock Phase Refer to SPI Transfer Format.
SCK CYCLE # SCK (CPOL = 0) SCK (CPOL = 1) SAMPLE INPUT (CPHA = 0) DATA OUT SAMPLE INPUT (CPHA = 1) DATA OUT SS (TO SLAVE) SLAVE CPHA=1 TRANSFER IN PROGRESS 3 MASTER TRANSFER IN PROGRESS 2 1 1. SS ASSERTED 2. MASTER WRITES TO SPDR 3. FIRST SCK EDGE 4. SPIF SET 5. SS NEGATED
SPI TRANSFER FORMAT 1
1
2
3
4
5
6
7
8
MSB
6
5
4
3
2
1
LSB
MSB
6
5
4
3
2
1
LSB
4 SLAVE CPHA=0 TRANSFER IN PROGRESS 5
Figure 13 SPI Transfer Format
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 45
NOTE This figure shows transmission order when LSBF = 0 default. If LSBF = 1, data is transferred in reverse order (LSB first). SPR2, SPR1 and SPR0 -- SPI Clock Rate Selects (SPR2 is located in OPT2 register)
SPR[2:0] 000 001 010 011 100 101 110 111 Divide E Clock By 2 4 16 32 8 16 64 128 Frequency at E = 2 MHz (Baud) 1.0 MHz 500 kHz 125 kHz 62.5 kHz 250 kHz 125 kHz 31.3 kHz 15.6 kHz
SPSR --Serial Peripheral Status Register
Bit 7 SPIF RESET: 0 6 WCOL 0 5 -- 0 4 MODF 0 3 -- 0 2 -- 0 1 -- 0
$0029
Bit 0 -- 0
SPIF -- SPI Transfer Complete Flag This flag is set when an SPI transfer is complete (after eight SCK cycles in a data transfer). Clear this flag by reading SPSR (with SPIF = 1), then access SPDR data register. 0 = No SPI transfer complete or SPI transfer still in progress 1 = SPI transfer complete WCOL -- Write Collision This flag is set if the MCU tries to write data into SPDR while an SPI data transfer is in progress. Clear this flag by reading SPSR (WCOL = 1), then access SPDR. 0 = No write collision 1 = Write collision Bit 5 -- Not implemented Always reads zero MODF -- Mode Fault (Mode fault terminates SPI operation) 0 = No mode fault 1 = Mode fault (SS is pulled low while MSTR = 1) Bits [3:0] -- Not implemented Always read zero SPDR --SPI Data
Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1
$002A
Bit 0 Bit 0
SPI is double buffered in, single buffered out.
MOTOROLA 46
MC68HC11KA4 MC68HC11KA4TS/D
OPT2 --System Configuration Options 2
Bit 7 LIRDV RESET: 0 6 CWOM 0 5 -- 0 4 IRVNE -- 3 LSBF 0 2 SPR2 0 1 XDV1 0
$0038
Bit 0 XDV0 0
LIRDV-- LIR Driven Refer to 2 Operating Modes and On-Chip Memory. CWOM -- Port C Wired-OR Mode Refer to 6 Parallel Input/Output. Bit 5 -- Not implemented Always reads zero IRVNE -- Internal Read Visibility/Not E Refer to 2 Operating Modes and On-Chip Memory. LSBF -- SPI LSB First Enable 0 = SPI data transferred MSB first 1 = SPI data transferred LSB first SPR2 -- SPI Clock (SCK) Rate Select Adds a divide by four prescaler to SPI clock chain. Refer to SPCR register. XDV[1:0] -- XOUT Clock Divide Select Refer to 2 Operating Modes and On-Chip Memory.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 47
9 Analog-to-Digital Converter
The analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. The MC68HC11KA4/KA2 A/D converter system is an 8-channel (four channels on 64-pin version), 8-bit, multiplexed-input, successive-approximation converter. It does not require external sample and hold circuits. The sample and hold time is 12 clock cycles. Refer to Figure 15. The clock source for the A/D converter's charge pump, like the clock source for the EEPROM charge pump, is selected with the CSEL bit in the OPTION register. When the E clock is slower than 1 MHz, the CSEL bit must be set to ensure that the successive approximation sequence for the A/D converter will be completed before any charge loss occurs. In the case of the EEPROM, it is the efficiency of the charge pump that is affected.
PE0 AN0 PE1 AN1 PE2 AN2 PE3 AN3 PE4 AN4 PE5 AN5 PE6 AN6 ANALOG MUX 8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD
VRH
VRL
SUCCESSIVE APPROXIMATION REGISTER AND CONTROL RESULT
INTERNAL DATA BUS
CCF
SCAN MULT CD CC CB
PE7 AN7
ADCTL A/D CONTROL
RESULT REGISTER INTERFACE
ADR1 A/D RESULT 1
ADR2 A/D RESULT 2
ADR3 A/D RESULT 3
ADR4 A/D RESULT 4
CA
EA9 A/D BLOCK
Figure 14 A/D Converter Block Diagram The A/D converter can operate in single or multiple conversion modes. Multiple conversions are performed in sequences of four. Sequences can be performed on a single channel or on a group of channels.
MOTOROLA 48
MC68HC11KA4 MC68HC11KA4TS/D
Pins AVDD and AVSS provide the supply voltage to the digital portion of the A/D converter. Pins VRH and VRL provide the reference supply voltage inputs. A multiplexer allows the single A/D converter to select one of 16 analog input signals. Refer to the A/D converter channel assignment bits CD-CA description. The A/D converter control logic implements automatic conversion sequences on a selected channel four times or on a group of four channels once each. A write to the ADCTL register initiates conversions and, if made while a conversion is in process, a write to ADCTL also halts a conversion operation in progress. When the MULT bit is zero, the A/D converter system is configured to perform four consecutive conversions on the single channel specified by the four channel-select bits (CD-CA). When the MULT bit is one, the A/D system is configured to perform conversions on each channel in the group of four channels specified by the CD and CC channel select bits. Refer to Table 8. When the SCAN bit is zero, four conversions are performed in the desired channel group, once each, to fill the four result registers. When SCAN is one, conversions continue channel-by-channel in the desired group with the result registers being updated continually as new data becomes available.
E CLOCK MSB 4 CYCLES BIT 6 2 CYC BIT 5 2 CYC BIT 4 2 CYC BIT 3 2 CYC BIT 2 2 CYC BIT 1 2 CYC LSB 2 CYC 2 CYC END
12 E CYCLES WRITE TO ADCTL
SAMPLE ANALOG INPUT
SUCCESSIVE APPROXIMATION SEQUENCE
0
CONVERT FIRST CHANNEL, UPDATE ADR1
32
CONVERT SECOND CHANNEL, UPDATE ADR2
64
CONVERT THIRD CHANNEL, UPDATE ADR3
96
CONVERT FOURTH CHANNEL, UPDATE ADR4
128 -- E CYCLES
A/D CONVERSION TIM
Figure 15 Timing Diagram for a Sequence of Four A/D Conversions
ANALOG INPUT PIN
DIFFUSION/POLY COUPLER + ~20V - ~0.7V + ~12V - ~0.7V
DUMMY N-CHANNEL OUTPUT DEVICE
4 K 400 nA JUNCTION LEAKAGE
*
~ 20 pF DAC CAPACITANCE
< 2 pF
INPUT PROTECTION DEVICE
VRL
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
ANALOG INPUT PIN
Figure 16 Electrical Model of an Analog Input Pin (Sample Mode)
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 49
REPEAT SEQUENCE, SCAN = 1
SET CC FLAG
ADCTL --A/D Control/Status
Bit 7 CCF RESET: 0 6 -- 0 5 SCAN 0 4 MULT 0 3 CD 0 2 CC 0 1 CB 0
$0030
Bit 0 CA 0
CCF -- Conversions Complete Flag CCF is set after an A/D conversion cycle and cleared when ADCTL is written. Bit 6 -- Not implemented Always reads zero SCAN -- Continuous Scan Control 0 = Do four conversions and stop 1 = Convert four channels in selected group continuously MULT -- Multiple Channel/Single Channel Control 0 = Convert single channel selected 1 = Convert four channels in selected group CD-CA -- Channel Select D through A Table 8 A/D Converter Channel Assignments
Channel Select Control Bits CD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Channel Signal AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved Reserved Reserved Reserved VRH* VRL* (VRH)/2* Reserved* Result in ADRx if MULT = 1 ADR1 ADR2 ADR3 ADR4 ADR1 ADR2 ADR3 ADR4 -- -- -- -- ADR1 ADR2 ADR3 ADR4
*Used for factory testing
ADR[4:1] --A/D Results
$0031 $0032 $0033 $0034 Bit 7 Bit 7 Bit 7 Bit 7 6 6 6 6 5 5 5 5 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1
$0031-$0034
Bit 0 Bit 0 Bit 0 Bit 0 ADR1 ADR2 ADR3 ADR4
MOTOROLA 50
MC68HC11KA4 MC68HC11KA4TS/D
OPTION --System Configuration Options
Bit 7 ADPU RESET: 0 6 CSEL 0 5 IRQE* 0 4 DLY* 1 3 CME 0 2 FCME* 0 1 CR1* 0
$0039
Bit 0 CR0* 0
*Can be written only once in first 64 cycles out of reset in normal modes, any time in special mode.
ADPU -- A/D Converter Power-Up 0 = A/D converter powered down 1 = A/D converter powered up CSEL -- Clock Select 0 = A/D and EEPROM use system E clock 1 = A/D and EEPROM use internal RC clock source IRQE -- IRQ Select Edge Sensitive Only Refer to 5 Resets and Interrupts. DLY -- Enable Oscillator Start-up Delay on Exit from Stop Refer to 5 Resets and Interrupts. CME -- Clock Monitor Enable Refer to 5 Resets and Interrupts. FCME -- Force Clock Monitor Enable Refer to 5 Resets and Interrupts. CR[1:0] -- COP Timer Rate Select Refer to 5 Resets and Interrupts.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 51
10 Main Timer
The timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler. A timer overflow function allows software to extend the system's timing capability beyond the counter's 16-bit range. The timer has three channels of input capture, four channels of output compare, and one channel that can be configured as a fourth input capture or a fifth output compare. In addition, the timing system includes pulse accumulator and real-time interrupt (RTI) functions, as well as a clock monitor function, which can be used to detect clock failures that are not detected by the COP. Refer to 11 Pulse Accumulator and 10.1 Real-Time Interrupt for further information about these functions. Refer to the following table for a summary of the crystal-related frequencies and periods. Table 9 Timer Summary
XTAL Frequencies 8.0 MHz Control Bits PR[1:0] 00 1 count -- overflow -- 01 1 count -- overflow -- 10 1 count -- overflow -- 11 1 count -- overflow -- RTR[1:0] 00 01 10 11 CR[1:0] 00 01 10 11 Time-out Tolerance (-0 ms/+...) 16.384 ms 65.536 ms 262.14 ms 1.049 s 4.096 ms 8.192 ms 16.384 ms 32.768 ms 500 ns 32.768 ms 2.0 s 131.07 ms 4.0 s 262.14 ms 8.0 s 524.29 ms 2.0 MHz 500 ns 12.0 MHz 3.0 MHz 333 ns 16.0 MHz 4.0 MHz 250 ns Other Rates (E) (1/E)
Main Timer Count Rates 333 ns 21.845 ms 1.333 s 87.381 ms 2.667 s 174.76 ms 5.333 s 349.52 ms 2.731 ms 5.461 ms 10.923 ms 21.845 ms 250 ns 16.384 ms 1.0 s 65.536 ms 2.0 s 131.07 ms 4.0 s 262.14 ms 2.048 ms 4.096 ms 8.192 ms 16.384 ms (E/1) (E/216) (E/4) (E/218) (E/8) (E/219) (E/16) (E/220) (E/213) (E/214 ) (E/215) (E/216) (E/215) (E/217 ) 19) (E/2 (E/221) (E/215)
Periodic (RTI) Interrupt Rates
COP Watchdog Time-out Rates 10.923 ms 43.691 ms 174.76 ms 699.05 ms 8.192 ms 32.768 ms 131.07 ms 524.28 ms
16.4 ms
10.9 ms
8.192 ms
MOTOROLA 52
MC68HC11KA4 MC68HC11KA4TS/D
PRESCALER-DIVIDE BY MCU ECLK 1, 4, 8, OR 16 PR1 PR0
TCNT (HI)
TCNT (LO)
TOI TOF
16-BIT FREE-RUNNING COUNTER
9
TO PULSE ACCUMULATOR
TAPS FOR RTI, COP WATCHDOG AND PULSE ACCUMULATOR TMSK1 OC1I TFLG1
INTERRUPT REQUESTS (FURTHER QUALIFIED BY I-BIT IN CCR) PIN FUNCTIONS 8 BIT-7 PA7/ OC1/ PAI
16-BIT TIMER BUS
16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO)
CFORC
OC1F FOC1 OC2I 7
16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO)
OC2F FOC2 OC3I 6
BIT-6
PA6/ OC2/ OC1
16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO)
OC3F FOC3 OC4I 5
BIT-5
PA5/ OC3/ OC1
16-BIT TIMER BUS
16-BIT COMPARATOR = TOC4 (HI) TOC4 (LO)
OC4F FOC4 I4/O5I 4 PA3 OC5/ IC4/ OC1 BIT-4 PA4/ OC4/ OC1
16-BIT COMPARATOR = TI4/O5 (HI) TI4/O5 (LO) 16-BIT LATCH CLK
OC5 I4/O5F FOC5 IC4 FORCE OUTPUT COMPARE BIT-3
I4/O5
IC1I
3
BIT-2
PA2/ IC1
16-BIT LATCH CLK TIC1 (HI) TIC1 (LO)
IC1F
IC2I 16-BIT LATCH CLK TIC2 (HI) TIC2 (LO) IC2F
2
BIT-1
PA1/ IC2
IC3I 16-BIT LATCH CLK TIC3 (HI) TIC3 (LO) IC3F STATUS FLAGS INTERRUPT ENABLES
1
BIT-0
PA0/ IC3
PORT A PIN CONTROL
Figure 17 Timer Block Diagram
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 53
CFORC -- Timer Compare Force
Bit 7 FOC1 RESET: 0 6 FOC2 0 5 FOC3 0 4 FOC4 0 3 FOC5 0 2 -- 0 1 -- 0
$000B
Bit 0 -- 0
FOC[5:1] -- Force Output Comparison When the FOC bit associated with an output compare circuit is set, the output compare circuit immediately performs the action it is programmed to do when an output match occurs. 0 = Not affected 1 = Output x action occurs Bits [2:0] -- Not implemented Always read zero OC1M -- Output Compare 1 Mask
Bit 7 OC1M7 RESET: 0 6 OC1M6 0 5 OC1M5 0 4 OC1M4 0 3 OC1M3 0 2 -- 0 1 -- 0
$000C
Bit 0 -- 0
Set bit(s) to enable OC1 to control corresponding pin(s) of port A Bits [2:0] -- Not implemented Always read zero OC1D -- Output Compare 1 Data
Bit 7 OC1D7 RESET: 0 6 OC1D6 0 5 OC1D5 0 4 OC1D4 0 3 OC1D3 0 2 -- 0 1 -- 0
$000D
Bit 0 -- 0
If OC1Mx is set, data in OC1Dx is output to port A bit x on successful OC1 compares. Bits [2:0] -- Not implemented Always read zero TCNT -- Timer Count
$000E $000F Bit 15 Bit 7 14 6 13 5 12 4 11 3 10 2 9 1 Bit 8 Bit 0
$000E, $000F
High Low TCNT
TCNT resets to $0000. In normal modes, TCNT is read-only. TIC1-TIC3 --Timer Input Capture
$0010 $0011 $0012 $0013 $0014 $0015 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 14 6 14 6 14 6 13 5 13 5 13 5 12 4 12 4 12 4 11 3 11 3 11 3 10 2 10 2 10 2 9 1 9 1 9 1 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
$0010-$0015
High Low High Low High Low TIC3 TIC2 TIC1
TICx not affected by reset
MOTOROLA 54
MC68HC11KA4 MC68HC11KA4TS/D
TOC1-TOC4 --Timer Output Compare
$0016 $0017 $0018 $0019 $001A $001B $001C $001D Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 14 6 14 6 14 6 14 6 13 5 13 5 13 5 13 5 12 4 12 4 12 4 12 4 11 3 11 3 11 3 11 3 10 2 10 2 10 2 10 2 9 1 9 1 9 1 9 1 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0
$0016-$001D
High Low High Low High Low High Low TOC4 TOC3 TOC2 TOC1
All TOCx register pairs reset to ones ($FFFF). TI4/O5 -- Timer Input Capture 4/Output Compare 5
$001E $001F Bit 15 Bit 7 14 6 13 5 12 4 11 3 10 2 9 1
$001E, $001F
Bit 8 Bit 0 High Low
This is a shared register and is either input capture 4 or output compare 5 depending on the state of bit I4/O5 in PACTL. Writes to TI4/O5 have no effect when this register is configured as input capture 4. All TI4/O5 register pairs reset to ones ($FFFF). TCTL1 -- Timer Control 1
Bit 7 OM2 RESET: 0 6 OL2 0 5 OM3 0 4 OL3 0 3 OM4 0 2 OL4 0 1 OM5 0
$0020
Bit 0 OL5 0
OM[5:2] -- Output Mode OL[5:2] -- Output Level
OMx 0 0 1 1 OLx 0 1 0 1 Action Taken on Successful Compare Timer disconnected from output pin logic Toggle OCx output line Clear OCx output line to 0 Set OCx output line to 1
TCTL2 -- Timer Control 2
Bit 7 EDG4B RESET: 0 6 EDG4A 0 5 EDG1B 0 4 EDG1A 0 3 EDG2B 0 2 EDG2A 0 1 EDG3B 0
$0021
Bit 0 EDG3A 0
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 55
Table 10 Timer Control Configuration
EDGxB 0 0 1 1 EDGxA 0 1 0 1 Configuration Capture disabled Capture on rising edges only Capture on falling edges only Capture on any edge
TMSK1 -- Timer Interrupt Mask 1
Bit 7 OC1I RESET: 0 6 OC2I 0 5 OC3I 0 4 OC4I 0 3 I4/O5I 0 2 IC1I 0 1 IC2I 0
$0022
Bit 0 IC3I 0
OC1I-OC4I -- Output Compare x Interrupt Enable I4/O5I -- Input Capture 4 or Output Compare 5 Interrupt Enable IC1I-IC3I -- Input Capture x Interrupt Enable NOTE Control bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable the corresponding interrupt sources. TFLG1 -- Timer Interrupt Flag 1
Bit 7 OC1F RESET: 0 6 OC2F 0 5 OC3F 0 4 OC4F 0 3 I4/O5F 0 2 IC1F 0 1 IC2F 0
$0023
Bit 0 IC3F 0
Clear flags by writing a one to the corresponding bit position(s). OC1F-OC4F -- Output Compare x Flag Set each time the counter matches output compare x value I4/O5F -- Input Capture 4/Output Compare 5 Flag Set by IC4 or OC5, depending on which function was enabled by I4/O5 bit in PACTL IC1F-IC3F -- Input Capture x Flag Set each time a selected active edge is detected on the ICx input line TMSK2 --Timer Interrupt Mask 2
Bit 7 TOI RESET: 0 6 RTII 0 5 PAOVI 0 4 PAII 0 3 -- 0 2 -- 0 1 PR1 0
$0024
Bit 0 PR0 0
TOI -- Timer Overflow Interrupt Enable 0 = Timer overflow interrupt disabled 1 = Timer overflow interrupt enabled RTII -- Real-Time Interrupt Enable 0 = RTIF interrupts disabled 1 = Interrupt requested when RTIF is set to one.
MOTOROLA 56
MC68HC11KA4 MC68HC11KA4TS/D
NOTE Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. PAOVI -- Pulse Accumulator Overflow Interrupt Enable Refer to 11 Pulse Accumulator. PAII -- Pulse Accumulator Interrupt Enable Refer to 11 Pulse Accumulator. Bits [3:2] -- Not implemented Always read zero PR[1:0] -- Timer Prescaler Select In normal modes, PR1 and PR0 can only be written once, and the write must occur within 64 cycles after reset. Refer to 10.1 Real-Time Interrupt for specific timing values.
PR[1:0] 00 01 10 11 Prescaler 1 4 8 16
TFLG2 -- Timer Interrupt Flag 2
Bit 7 TOF RESET: 0 6 RTIF 0 5 PAOVF 0 4 PAIF 0 3 -- 0 2 -- 0 1 -- 0
$0025
Bit 0 -- 0
Clear flags by writing a one to the corresponding bit position(s). TOF -- Timer Overflow Flag Set when TCNT changes from $FFFF to $0000 RTIF -- Real-Time (Periodic) Interrupt Flag Set periodically. Refer to RTR[1:0] bits in PACTL register. PAOVF -- Pulse Accumulator Overflow Flag Refer to 11 Pulse Accumulator. PAIF -- Pulse Accumulator Input Edge Flag Refer to 11 Pulse Accumulator. Bits [3:0] -- Not implemented Always read zero
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 57
PACTL --Pulse Accumulator Control
Bit 7 -- RESET: 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 -- 0 2 I4/O5 0 1 RTR1 0
$0026
Bit 0 RTR0 0
Bit 7 -- Not implemented Always reads zero PAEN -- Pulse Accumulator System Enable Refer to 11 Pulse Accumulator. PAMOD -- Pulse Accumulator Mode Refer to 11 Pulse Accumulator. PEDGE -- Pulse Accumulator Edge Control Refer to 11 Pulse Accumulator. Bit 3 -- Not implemented Always reads zero I4/O5 -- Input Capture 4/Output Compare 5 Configure TI4/O5 for input capture or output compare 0 = OC5 enabled 1 = IC4 enabled RTR[1:0] -- Real-Time Interrupt (RTI) Rate Refer to 10.1 Real-Time Interrupt. 10.1 Real-Time Interrupt The real-time interrupt (RTI) function can generate interrupts at different fixed periodic rates. These rates are a function of the MCU oscillator frequency and the value of the software-accessible control bits, RTR1 and RTR0. These bits determine the rate at which interrupts are requested by the RTI system. The RTI system is driven by an E divided by 213 rate clock compensated so that it is independent of the timer prescaler. The RTR1 and RTR0 control bits select an additional division factor. RTI is set to its fastest rate by default out of reset and can be changed at any time. Refer to interrupt enable and flag bits in TMSK2 and TFLG2 registers. Table 11 Real-Time Interrupt Rates
RTR [1:0] 00 01 10 11 Divide E By 213 214 215 216 E= XTAL = 8.0 MHz 4.096 ms 8.192 ms 16.384 ms 32.768 ms 2.0 MHz XTAL = 12.0 MHz 2.731 ms 5.461 ms 10.923 ms 21.845 ms 3.0 MHz XTAL = 16.0 MHz 2.048 ms 4.096 ms 8.192 ms 16.384 ms 4.0 MHz
MOTOROLA 58
MC68HC11KA4 MC68HC11KA4TS/D
11 Pulse Accumulator
The MC68HC11KA4/KA2 has an 8-bit counter that can be configured as a simple event counter or for gated time accumulation. The counter can be read or written at any time. The port A bit 7 I/O pin can be configured to act as a clock in event counting mode, or as a gate signal to enable a free-running clock (E divided by 64) to the 8-bit counter in gated time accumulation mode.
Selected Crystal CPU Clock Cycle Time (E/26) (E/214) (E) (1/E) 1 count -- overflow -- 8.0 MHz 2.0 MHz 500 ns
Common XTAL Frequencies 12.0 MHz 3.0 MHz 333 ns 21.330 s 5.461 ms 16.0 MHz 4.0 MHz 250 ns 16.0 s 4.096 ms
Pulse Accumulator (Gated Mode) 32.0 s 8.192 ms
PAOVI PAOVF
1 INTERRUPT REQUESTS 2
PAII PAIF PAOVI PAII PAOVF PAIF TFLG2 INTERRUPT STATUS PAI EDGE PAEN E / 64 CLOCK (FROM MAIN TIMER)
TMSK2 INT ENABLES
DISABLE FLAG SETTING OVERFLOW
PIN PA7/ PAI/ OC1 INPUT BUFFER AND EDGE DETECTOR OUTPUT BUFFER FROM MAIN TIMER OC1 FROM DDRA7 DATA BUS
2:1 MUX
CLOCK
PACNT 8-BIT COUNTER ENABLE
PAEN
PAEN PAMOD PEDGE PACTL CONTROL
INTERNAL DATA BUS
Figure 18 Pulse Accumulator System Block Diagram
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 59
TMSK2 --Timer Interrupt Mask 2
Bit 7 TOI RESET: 0 6 RTII 0 5 PAOVI 0 4 PAII 0 3 -- 0 2 -- 0 1 PR1 0
$0024
Bit 0 PR0 0
TOI -- Timer Overflow Interrupt Enable Refer to 10 Main Timer. RTII -- Real-Time Interrupt Enable Refer to 10 Main Timer. PAOVI -- Pulse Accumulator Overflow Interrupt Enable 0 = Pulse accumulator overflow interrupt disabled 1 = Pulse accumulator overflow interrupt enabled PAII -- Pulse Accumulator Input Interrupt Enable 0 = Pulse accumulator input interrupt disabled 1 = Pulse accumulator input interrupt enabled if PAIF bit in TFLG2 register is set Bits [3:2] -- Not implemented Always read zero PR[1:0] -- Timer Prescaler Select Refer to 10 Main Timer. NOTE Control bits [7:4] in TMSK2 correspond bit for bit with flag bits [7:4] in TFLG2. Ones in TMSK2 enable the corresponding interrupt sources. TFLG2 --Timer Interrupt Flag 2
Bit 7 TOF RESET: 0 6 RTIF 0 5 PAOVF 0 4 PAIF 0 3 -- 0 2 -- 0 1 -- 0
$0025
Bit 0 -- 0
Clear flags by writing a one to the corresponding bit position(s). TOF -- Timer Overflow Enable Refer to 10 Main Timer. RTIF -- Real-Time Interrupt Flag Refer to 10 Main Timer. PAOVF -- Pulse Accumulator Overflow Flag Set when PACNT changes from $FF to $00 PAIF -- Pulse Accumulator Input Edge Flag Set each time a selected active edge is detected on the PAI input line Bits [3:0] -- Not implemented Always read zero
MOTOROLA 60
MC68HC11KA4 MC68HC11KA4TS/D
PACTL --Pulse Accumulator Control
Bit 7 -- RESET: 0 6 PAEN 0 5 PAMOD 0 4 PEDGE 0 3 -- 0 2 I4/O5 0 1 RTR1 0
$0026
Bit 0 RTR0 0
Bit 7 -- Not implemented Always reads zero PAEN -- Pulse Accumulator System Enable 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled PAMOD -- Pulse Accumulator Mode 0 = Event counter 1 = Gated time accumulation PEDGE -- Pulse Accumulator Edge Control 0 = In event mode, falling edges increment counter. In gated accumulation mode, high level enables accumulator and falling edge sets PAIF. 1 = In event mode, rising edges increment counter. In gated accumulation mode, low level enables accumulator and rising edge sets PAIF. Bit 3 -- Not implemented Always reads zero I4/O5 -- Input Capture 4/Output Compare 5 Refer to 10 Main Timer. RTR[1:0] -- Real-Time Interrupt Rate Refer to 10 Main Timer. PACNT --Pulse Accumulator Counter
Bit 7 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1
$0027
Bit 0 Bit 0
Can be read and written.
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 61
12 Pulse-Width Modulation Timer
The MC68HC11KA4/KA2 MCU contains a PWM timer that is composed of a four-channel 8-bit modulator. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM provides up to four pulse-width modulated waveforms on specific port H pins. Each channel has its own counter. Pairs of counters can be concatenated to create 16-bit PWM outputs based on 16bit counts. Three clock sources (A, B, and S) give the PWM a wide range of frequencies. Four control registers configure the PWM outputs -- PWCLK, PWPOL, PWSCAL, and PWEN. The PWCLK register selects the prescale value for PWM clock sources and enables the 16-bit counters. The PWPOL register determines each channel's polarity and selects the clock source for each channel. The PWSCAL register derives a user-scaled clock, based on the A clock source, and the PWEN register enables the PWM channels. Each channel has a separate 8-bit counter, period register, and duty cycle register. The period and duty cycle registers are double buffered so that if they are changed while the channel is enabled, the change does not take effect until the counter rolls over or the channel is disabled. With channels configured for 8-bit mode and E = 4 MHz, PWM signals of 40 kHz (1% duty cycle resolution) to less than 10 Hz (approximately 0.4% duty cycle resolution) can be produced. By configuring the channels for 16-bit mode with E = 4 MHz, PWM periods greater than one minute are possible. In 16-bit mode, duty cycle resolution of almost 15 parts per million can be achieved (at a PWM frequency of about 60 Hz). In the same system, a PWM frequency of 1 kHz corresponds to a duty cycle resolution of 0.025%.
MOTOROLA 62
MC68HC11KA4 MC68HC11KA4TS/D
MCU E CLOCK
/1 /2 /4 /8 / 16 / 32 / 64 / 128
PCKB1 PCKB2 PCKB3
8-BIT COMPARE = PWSCAL 8 RESET
/2
CLOCK S
SELECT
8-BIT COUNTER
PCKA1 PCKA2 SELECT PCLK3 PCLK4 CLOCK B PWEN3 PWEN4 CON34
CLOCK A
CLOCK SELECT CNT3 CNT4
PCLK1 PCLK2
CLOCK SELECT CNT1 CNT2
PWEN1 PWEN2 CON12
PWCNT1 RESET
PWCNT2 RESET
CARRY
CON12 S
PPOL1 Q MUX BIT 0 Q
8 8-BIT COMPARE = PWPER1 8-BIT COMPARE = PWDTY1
8 8-BIT COMPARE = PWPER2 8-BIT COMPARE = PWDTY2
16-BIT PWM CONTROL
R
PH0/ PW1
S R
Q MUX Q PPOL2 PORT H PIN CONTROL BIT 1 PH1/ PW2
PWCNT3 RESET
PWCNT4 RESET
CARRY
CON34 S
PPOL3 Q MUX BIT 2 Q
8 8-BIT COMPARE = PWPER3 8-BIT COMPARE = PWDTY3
8 8-BIT COMPARE = PWPER4 8-BIT COMPARE = PWDTY4
16-BIT PWM CONTROL
R
PH2/ PW3
S R
Q MUX Q PPOL4 BIT 3 PH3/ PW4
PWM OUTPUT PWDTY PWPER
Figure 19 Pulse Width Modulation Block Diagram
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 63
PWCLK --Pulse-Width Modulation Clock Select
Bit 7 CON34 RESET: 0 6 CON12 0 5 PCKA2 0 4 PCKA1 0 3 -- 0 2 PCKB3 0 1 PCKB2 0
$0060
Bit 0 PCKB1 0
CON34 --Concatenate Channels 3 and 4 Channel 3 is high-order byte, and channel 4 (port H, bit 3) is output. Clock source is determined by PCLK4. 0 = Channels 3 and 4 are separate 8-bit PWMs. 1 = Channels 3 and 4 are concatenated to create one 16-bit PWM channel. CON12 --Concatenate Channels One and Two Channel 1 is high order byte, and channel 2 (port H, bit 1) is output. Clock source is determined by PCLK2. 0 = Channels 1 and 2 are separate 8-bit PWMs 1 = Channels 1 and 2 are concatenated to create one 16-bit PWM channel. PCKA[2:1] --Prescaler for Clock A (See also PWSCAL register) Determines the rate of clock A
PCKA[2:1] 00 01 10 11 Value of Clock A E E/2 E/4 E/8
Bit 3 -- Not implemented Always reads zero PCKB[3:1] -- Prescaler for Clock B Determines the rate for clock B
PCKB[3:1] 000 001 010 011 100 101 110 111 Value of Clock B E E/2 E/4 E/8 E/16 E/32 E/64 E/128
MOTOROLA 64
MC68HC11KA4 MC68HC11KA4TS/D
PWPOL --Pulse-Width Modulation Timer Polarity
Bit 7 PCLK4 RESET: 0 6 PCLK3 0 5 PCLK2 0 4 PCLK1 0 3 PPOL4 0 2 PPOL3 0 1 PPOL2 0
$0061
Bit 0 PPOL1 0
PCLK4 -- Pulse-Width Channel 4 Clock Select 0 = Clock B is source 1 = Clock S is source PCLK3 -- Pulse-Width Channel 3 Clock Select 0 = Clock B is source 1 = Clock S is source PCLK2 -- Pulse-Width Channel 2 Clock Select 0 = Clock A is source 1 = Clock S is source PCLK1 -- Pulse-Width Channel 1 Clock Select 0 = Clock A is source 1 = Clock S is source PPOL[4:1] -- Pulse-Width Channel x Polarity 0 = PWM channel x output is low at the beginning of the clock cycle and goes high when duty count is reached 1 = PWM channel x output is high at the beginning of the clock cycle and goes low when duty count is reached PWSCAL -- Pulse-Width Modulation Timer Prescaler
Bit 7 7 RESET: 0 6 6 0 5 5 0 4 4 0 3 3 0 2 2 0 1 1 0
$0062
Bit 0 0 0
Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result by 2. If PWSCAL = $00, divide clock A by 256, then divide the result by 2. PWEN -- Pulse-Width Modulation Timer Enable
Bit 7 TPWSL RESET: 0 6 DISCP 0 5 -- 0 4 -- 0 3 PWEN4 0 2 PWEN3 0 1 PWEN2 0
$0063
Bit 0 PWEN1 0
TPWSL -- PWM Scaled Clock Test Bit (TEST) DISCP -- Disable Compare Scaled E Clock (TEST) Bits [5:4] -- Not implemented Always read zero PWEN[1:4] -- Pulse-Width Channel 1-4 0 = Channel disabled 1 = Channel enabled
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 65
PWCNT[1:4] -- Pulse-Width Modulation Timer Counter 1 to 4
$0064 $0065 $0066 $0067 RESET: Bit 7 Bit 7 Bit 7 Bit 7 0 6 6 6 6 0 5 5 5 5 0 4 4 4 4 0 3 3 3 3 0 2 2 2 2 0 1 1 1 1 0
$0064-$0067
Bit 0 Bit 0 Bit 0 Bit 0 0 PWCNT1 PWCNT2 PWCNT3 PWCNT4
PWCNT[1:4] Begins count using whichever clock was selected PWPER[1:4] --Pulse-Width Modulation Timer Period 1 to 4
$0068 $0069 $006A $006B RESET: Bit 7 Bit 7 Bit 7 Bit 7 1 6 6 6 6 1 5 5 5 5 1 4 4 4 4 1 3 3 3 3 1 2 2 2 2 1 1 1 1 1 1
$0068-$006B
Bit 0 Bit 0 Bit 0 Bit 0 1 PWPER1 PWPER2 PWPER3 PWPER4
PWPER[1:4] Determines period of associated PWM channel PWDTY[1:4] -- Pulse-Width Modulation Timer Duty Cycle 1 to 4
Bit 7 $006C $006D $006E $006F RESET: Bit 7 Bit 7 Bit 7 Bit 7 1 6 6 6 6 6 1 5 5 5 5 5 1 4 4 4 4 4 1 3 3 3 3 3 1 2 2 2 2 2 1 1 1 1 1 1 1
$006C-$006F
Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 1 PWDTY1 PWDTY2 PWDTY3 PWDTY4
PWDTY[1:4] Determines duty cycle of associated PWM channel
MOTOROLA 66
MC68HC11KA4 MC68HC11KA4TS/D
MC68HC11KA4 MC68HC11KA4TS/D
MOTOROLA 67
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and B are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
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